Samsung Electronics Co., Ltd.

Kyoung-Sik Im

Han-Gu Kim

Suk-jin Kim

Jae-Hyok Ko

Chan-Hee Jeon

Il-Hun Son

Hyun-Jun Choi

A transistor with an electrical overstress (EOS) protection may include an active region, a plurality of impurity regions and a conduction pattern. The active region may be formed in a substrate. The impurity regions may be formed in the active region and arranged at a predetermined or given distance with respect to each other. The conduction pattern may be arranged between each of the impurity regions in a meandering shape, and the conduction pattern may include a center portion connected to a ground terminal. Therefore, a transistor with EOS protection, a clamp device, and an ESD protection circuit including the same may increase an on-time of a clamp device and may sufficiently discharge a charge due to the EOS by including a conduction pattern configured with gates that are connected with respect to each other in a meandering shape.

Transistor with EOS protection and ESD protection circuit including the same

A clamping circuit is provided, which may clamp a voltage at a node of a circuit to a stable level by using a transistor already included in the circuit. The clamping circuit may clamp a voltage at a first node of a circuit inside a semiconductor chip to a more stable level when electro-static discharge (ESD) occurs. The clamping circuit may include a transistor and a capacitive element to store a control voltage to turn on the transistor in response to ESD.

Voltage clamping circuits using MOS transistors and semiconductor chips having the same and methods of clamping voltages

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Yongin-si, South Korea

Kyoung-Sik Im