Samsung Electronics Co., Ltd.

Kyoung-Seok Kim

Han-Mei Choi

Hong-bae Park

Kong-Soo Lee

Jae-Jong Han

Young-Wook Park

Eun-Taek Yim

Ki-Hyun Hwang

Hyeon-Deok Lee

Seok-Woo Nam

In-Sung Park

Hyo-Jung Kim

Sang-Jin Park

Seung Mok Shin

Byung-Ho Ahn

Hwa-Sik Kim

Jae-Hyun Park

Young-sun Kim

Sung-Tae Kim

Ki-chul Kim

Jung-Hyun Lee

Young-wook Park

Jae-Soon Lim

Jae-Hee Oh

Chang-Hoon Lee

Ji-Hyun Jeong

Gab-Jin Nam

Bong-hyun Kim

Seung-Mok Shin

Dong-hun Han

Sung-Kwan Kang

Myeong-Jin Kim

Dong-Jo Kang

Sung-Eui Kim

Jong-wan Kwon

Beung-Keun Lee

Gi-Hyun Hwang

Yong-Geol Chung

Ko-Eun Lee

Disclosed is an image forming apparatus including a body housing in which an opening is formed for providing removal/mounting access of a removable cartridge; a door member for selectively closing the opening. The removable cartridge includes a cartridge status chip in which predetermined information relating to the removable cartridge is recorded. The door member of the image forming apparatus and the removable cartridge may each be provided with respective contact terminal or terminals that engage when the door member is closed with the removable cartridge received in the body housing of the image forming apparatus. The controller of the image forming apparatus uses the electrical continuity information of the contact terminal or terminals in order to determine the closure status of the door member and to control the operation of the image forming apparatus accordingly.

Image forming apparatus

Methods of forming integrated circuit devices include forming an etch stop layer on a surface of a semiconductor substrate and forming a first interlayer insulating layer on the etch stop layer. The first interlayer insulating layer is patterned to define an opening therein that exposes a first portion of the etch stop layer. This first portion of the etch stop layer is then removed to thereby expose an underlying portion of the surface of the semiconductor substrate. This removal of the etch stop layer may be performed by wet etching the first portion of the etch stop layer using a phosphoric acid solution. A semiconductor region is then selectively grown into the opening, using the exposed portion of the surface of the semiconductor substrate as an epitaxial seed layer.

Methods of forming integrated circuit devices having vertical semiconductor interconnects and diodes therein and devices formed thereby

A layer deposition method includes: feeding a reactant with a first flow of an inert gas as a carrier gas into a reaction chamber to chemisorb the reactant on a substrate; feeding the first flow of the inert gas to purge the reaction chamber and a first reactant feed line; and feeding the second flow of the inert gas into the reaction chamber through a feed line different from the first reactant feed line.

Layer deposition methods

The stacked semiconductor device includes a semiconductor substrate, a multi-layered insulation layer pattern having at least two insulation layer patterns and an opening, an active layer pattern formed on each of the insulation layer patterns, a first plug including single crystalline silicon-germanium, a second plug including single crystalline silicon, and a wiring electrically connected to the first plug and sufficiently filling up the opening. The insulation layer patterns are vertically stacked on the semiconductor substrate and the opening exposes an upper face of the semiconductor substrate. A side portion of the active layer pattern is exposed by the opening. The first plug is formed on the upper face of the semiconductor substrate to partially fill the opening. The second plug is partially formed on the first plug, and has substantially the same interface as that of the first plug.

Stacked semiconductor devices and methods of manufacturing the same

A method of forming a high dielectric film using atomic layer deposition (ALD), and a method of manufacturing a capacitor having the high dielectric film, include supplying a precursor containing a metal element to a semiconductor substrate and purging a reactor; supplying an oxidizer and purging the reactor; and supplying a reaction source containing nitrogen and purging the reactor.

Method of forming high dielectric film using atomic layer deposition and method of manufacturing capacitor having the high dielectric film

In a storage electrode of a semiconductor device, and a method of forming the same, the storage electrode includes an outer cylinder including a first outer cylindrical portion having a first outer diameter, and a second outer cylindrical portion that is formed on the first outer cylindrical portion and having a second outer diameter, which is less than the first outer diameter, the first and second outer cylindrical portions having substantially equal inner diameters, and an inner cylinder formed on inner surfaces of the outer cylinder.

Method of forming a storage electrode of a semiconductor device

Disclosed are a method for cleaning a deposition chamber by removing attached metal oxides, and a deposition apparatus for performing in situ cleaning. A first gas and a second gas are provided into the deposition chamber. The first gas is reacted with metal included in the metal oxide to generate reacting residues. The second gas then decomposes the reacting residues, and the decomposed residues are exhausted out of the chamber. Thus, this cleaning process can be rapidly accomplished while the deposition chamber is not opened or separated from a deposition apparatus.

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Storage electrode of a semiconductor device and method of forming the same

Disclosed is a method for forming a multi-layered structure having at least two films on a semiconductor substrate. The substrate is disposed on a thermally conductible stage for supporting the substrate. After the distance between the stage and the substrate is adjusted to a first interval so that the substrate has a first temperature by heat transferred from the stage, a first thin film is formed on the substrate at the first temperature. The distance is then adjusted from the first interval to a second interval so that the substrate reaches a second temperature, and then a second thin film is formed on the first thin film at the second temperature, thereby forming the multi-layered structure on the substrate. The multi-layered structure can be employed for a gate insulation film or the dielectric film of a capacitor.

Method for forming a multi-layered structure of a semiconductor device and methods for forming a capacitor and a gate insulation layer using the multi-layered structure

A plasma enhanced chemical vapor deposition apparatus and a method of forming a nitride layer using the same, wherein the plasma enhanced CVD apparatus includes a process chamber including an upper chamber with a dome shape, a lower chamber, and an insulator therebetween, a gas distributing ring, a susceptor for supporting a wafer and heating the process chamber, a plasma compensation ring surrounding the susceptor, a vacuum pump and an electric power source connected to the process chamber. The gas distributing ring has a plurality of upwardly inclined nozzles, allowing upward distribution of reactive gases. The method of forming a nitride layer includes forming a protective film on inner walls of a process chamber, the protective film having at least two layers of differeing dielectric constant, and sequentially supplying reactive gases to the process chamber. A nitride layer formed thereby has low hydrogen content, good density and oxidation resistance.

Plasma enhanced chemical vapor deposition apparatus and method for forming nitride layer using the same

A method of inhibiting pit occurrence on a semiconductor substrate during manufacture of a semiconductor device includes forming an isolation using a shallow trench isolation (STI) method in a semiconductor substrate, forming an insulation layer on an entire surface of the semiconductor substrate having the isolation, implanting ions into the semiconductor substrate using the insulation layer as a buffer layer, annealing the semiconductor substrate using a rapid thermal annealing (RTA) process, forming a photoresist layer on the insulation layer and then forming an opening in the photoresist layer to expose an underlayer thereof, forming an align key by etching the underlayer at the opening, and removing the photoresist layer and the insulation layer. Alternatively, the thickness of the insulation layer may be reduced to prevent the occurrence of pits on active areas of the semiconductor substrate.

Method of manufacturing a semiconductor device including alignment mark

Growing community of inventors

Seoul, South Korea

Kyoung-Seok Kim