Samsung Electronics Co., Ltd.

Furex Co., Ltd.

Kyoung-sei Choi

Sa-Yoon Kang

Si-hoon Lee

Kyong-Soon Cho

Donghan Kim

Yun-seok Choi

Jae-Wook Yoo

Byung-seo Kim

Ye-chung Chung

Young-sang Cho

Sang-Gui Jo

Eun-Seok Cho

Dae-woo Son

Sang-Heui Lee

Young-jae Joo

Jeong-kyu Ha

Hee-Seok Lee

Ji-Yong Park

Seok-Won Lee

Chul-Woo Kim

Jong-bo Shim

Pyoung-Wan Kim

Seung-Kon Mok

Jae-Hyok Ko

Kwan-Jai Lee

Mi-Na Choi

Hee-jung Hwang

Keung-beum Kim

Chang-Su Kim

Byoung-rim Seo

Jang-Woo Lee

Se-Ran Bae

Chang-soo Jin

Tae-weon Suh

Bo-Na Baek

Yoon-young Choi

Provided is an image sensor package that includes a transparent protection cover for protecting a plurality of unit pixels each including a microlens. The image sensor package includes a substrate which has a first surface and a second surface that are opposite to each other, and includes a sensor array region including a plurality of unit pixels formed in the first surface and a pad region including a pad arranged in the vicinity of the sensor array region, a plurality of microlenses formed on the plurality of unit pixels, respectively, at least two transparent material layers covering the plurality of microlenses, and a transparent protection cover attached onto the plurality of microlenses with the at least two transparent material layers interposed therebetween.

Image sensor package

Provided is semiconductor package, including a semiconductor chip; an upper structure over the semiconductor chip, the upper structure having a first thermal expansion coefficient; and a lower structure under the semiconductor chip, the lower structure having a second thermal expansion coefficient of less than or equal to the first thermal expansion coefficient.

Semiconductor package

A stack type semiconductor package includes: a lower semiconductor package including a lower package substrate, and a lower semiconductor chip which is mounted on the lower package substrate and includes a first surface facing a top surface of the lower package substrate and a second surface opposite to the first surface; an upper semiconductor package including an upper package substrate and an upper semiconductor chip which is mounted on the upper package substrate; an inter-package connection unit which connects the lower package substrate and the upper package substrate; a heat dissipation member which is formed on the second surface of the lower semiconductor chip; and an interconnection unit which is formed on a bottom surface of the upper package substrate, and is adhered to the heat dissipation member to connect the lower semiconductor chip and the upper package substrate.

Stack type semiconductor package

A method for forming a circuit pattern forming region in an insulating substrate may include preparing a metallic pattern, coating a polymer solution on a casting vessel, precuring the polymer solution, and forming an imprinted circuit pattern forming region in the precured polymer solution using the metallic pattern.

Methods for forming circuit pattern forming region in an insulating substrate

A heat sink includes a first adhesive layer, and a heat dissipation layer disposed on the first adhesive layer, and has ventilation ports that extend therethrough including through the first adhesive layer and the heat dissipation layer. The heat sink forms an outermost part of a semiconductor package. Thus, when the heat sink is bonded via its adhesive layer to underlying structure during a manufacturing process, the ventilation ports allow air to pass therethrough. As a result, air is not trapped in the form of bubbles between the heat sink and the underlying structure.

Flexible heat sink having ventilation ports and semiconductor package including the same

A structure of a semiconductor chip package is provided. The semiconductor chip package includes: a substrate; a semiconductor chip mounted on a first surface of the substrate; a plurality of electrode pads on a second surface, different from the first surface, of the substrate; and an electrostatic discharge protection pad overlapping a portion of a first electrode pad and a portion of a second electrode pad among the plurality of electrode pads.

Semiconductor chip package

A Chip on Flexible Printed Circuit (COF) type semiconductor package may include a flexible film, a semiconductor IC chip on the flexible film, and a heating pad on the flexible film.

Chip on flexible printed circuit type semiconductor package

Provided is an electromagnetic interference (EMI) removing device for active reduction of electromagnetic interference and a semiconductor package including the same. The EMI removing device may include a film substrate having an antenna pattern configured to generate a second electromagnetic wave, which may have substantially the same frequency band, modulation mode, and directivity as a first electromagnetic wave generated by a first semiconductor chip and a phase opposite to a phase of the first electromagnetic wave.

Device for removing electromagnetic interference and semiconductor package including the same

Provided is a wiring substrate, a semiconductor device package including the wiring substrate, and methods of fabricating the same. The semiconductor device package may include a wiring substrate which may include a base film. The base film may include a mounting region and a non-mounting region. The wiring substrate may further include first wiring patterns on the non-mounting region and extending into the mounting region, second wiring patterns on the first wiring patterns of the non-mounting region, and an insulating layer on the non-mounting region, and a semiconductor device which may include bonding pads. At least one of side surfaces of the second wiring patterns adjacent to the mounting region may be electrically connected to at least one of the bonding pads of the semiconductor device.

Method of fabricating a semiconductor device package

Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component.

Tape for heat dissipating member, chip on film type semiconductor package including heat dissipating member, and electronic apparatus including the same

A flexible substrate used in a semiconductor package, a method of manufacturing the same, and a semiconductor package including the flexible substrate. A circuit pattern forming region is formed in an insulating substrate with a dented shape and a circuit pattern formed of a metallic material is formed in the circuit pattern forming region.

Flexible substrate for a semiconductor package, method of manufacturing the same, and semiconductor package including flexible substrate

Flip chip packages and methods of manufacturing the same are provided, the flip chip packages may include a package substrate, a semiconductor chip, conductive bumps, a ground pattern and an underfilling layer. The semiconductor chip may be over the package substrate. The conductive bumps may be between the semiconductor chip and the package substrate to electrically connect the semiconductor chip and the package substrate with each other. The ground pattern may ground one of the package substrate and the semiconductor chip. The underfilling layer may be between the package substrate and the semiconductor chip to surround the conductive bumps. The underfilling layer may have a diode selectively located between the ground pattern and the conductive bumps by electrostatic electricity applied to the underfilling layer to protect the semiconductor chip from the electrostatic electricity.

Flip chip packages

A method of cutting a semiconductor wafer includes preparing a semiconductor wafer including a scribe region and a chip region, forming a groove in the scribe region, loading the semiconductor wafer with the groove formed therein in a chamber, and cutting the semiconductor wafer into a plurality of chips through increasing a pressure of the chamber by a first pressure change rate, and then reducing the pressure of the chamber by a second pressure change rate.

Growing community of inventors

Yongin-si, South Korea

Kyoung-sei Choi