Electronics and Telecommunications Research Institute

Lg Household & Health Care Ltd.

Kyoung Ran Park

Sang Min Lee

Sun-Wook Kim

Myung-Joon Kim

Kyung Hwan Kim

Jin-Young Moon

Jeun-Woo Lee

Dong Wan Kim

Kyu-Chang Kang

Ji Hee Yoo

Young Hyun Kim

Jeong Rae Lee

Seong Kil Son

Yong-Jin Kwon

Youngwoo Kim

Young Woo Kim

Myung Joon Kim

Seong Woon Kim

Dae-won Kim

Sang Man Moh

Chang-Seok Bae

Kee-Wook Rim

Yong Youn Kim

Jae Sung Lee

Seong-Woon Kim

Sung Nam Kim

Woo Jong Hahn

Kee Wook Rim

Chan-ho Park

Jong-Seok Han

Woo-Jong Hahn

Jong Seok Hahn

Won-Sae Sim

Jong-Youl Park

Won Ok Kwon

ChanHo Park

The present invention relates to a composition for surface modification. The composition for surface modification according to the present invention contains a particular carbodiimide-based compound, thus forms a covalent bond without damaging skin, hair, or fabric, and semipermanently provides desired skin or hair surface modification effects or fabric care effects.

Composition for surface modification

Disclosed herein are a video interpretation apparatus and method. The video interpretation apparatus includes an object information generation unit for generating object information based on objects in an input video, a relation generation unit for generating a dynamic spatial relation between the objects based on the object information, a general event information generation unit for generating general event information based on the dynamic spatial relation, a video information generation unit for generating video information including any one of a sentence and an event description based on the object information and the general event information, and a video descriptor storage unit for storing the object information, the general event information, and the video information.

Video interpretation apparatus and method

Disclosed herein are a query input apparatus and method. The query input apparatus includes: an input unit providing a graphic user interface (GUI) to receive a schematized composite activity that a user wants to search from the user; and a processing unit generating a query using an activity descriptor corresponding to the schematized composite activity depending on a query request from an activity searching system and transferring the generated query to the activity searching system.

Query input apparatus and method

An apparatus and method for providing primitive visual knowledge are disclosed. The method of providing primitive visual knowledge includes receiving an image in a form of a digital image sequence, dividing the received image into scenes, extracting a representative shot from each of the scenes, extracting objects from frames which compose the representative shot, extracting action verbs based on a mutual relationship between the extracted objects, selecting a frame best expressing the mutual relationship with the objects, which are the basis for the extracting of the action verbs, as a key frame, generating the primitive visual knowledge based on the selected key frame, storing the generated primitive visual knowledge in a database, and visualizing the primitive visual knowledge stored in the database to provide the primitive visual knowledge to a manager.

Apparatus and method for providing primitive visual knowledge

Provided is an apparatus for detection timeout of each channel, which is a socket connection, in a Transmission Control Protocol (TCP) Offload Engine (TOE) using TCP accelerating hardware, and a method thereof. The timer managing apparatus of the TOE using the TCP accelerating hardware, including: a command register for receiving a command for a retransmission timer or a delayed ACK timer from an embedded processor of the TOE; a finite state machine (FSM) for storing information of a timer in operation by analyzing the command for the retransmission timer or the delayed ACK timer stored in the command register and controlling an entire operation of the timer managing apparatus; and a timeout checker for checking timeout of a timer in operation by using the stored timer information and notifying the timeout to the FSM.

Retransmission and delayed ACK timer management logic for TCP protocol

Provided are a hardware device and method for transmitting a network protocol packet in a TOE for network protocol acceleration. The hardware device includes: a socket resource control and TCP connection/release command unit for storing socket resource control commands, and TCP connection/release commands from a host processor; a message transmission command storing unit for storing message transmission commands based on network protocol corresponding to each socket; a socket information and packet transmission information storing unit for storing socket information and packet transmission information; and a transmission-only processor for checking necessary transmission resources by interpreting message transmission commands stored in the message transmission command storing unit, processing a message to be transmitted in a form of a network packet, reading data to be transmitted, creating a header, and storing socket information and packet transmission information in the socket information and packet transmission information storing unit.

Hardware device and method for transmitting network protocol packet

Provided are an apparatus and method for transmitting a packet on Internet Protocol (IP) offload. The apparatus includes: an IP header creating unit for creating an IP header; an Address Resolution Protocol (ARP) request header creating unit for creating an ARP request header; an ARP response header creating unit for creating an ARP response header; a Transmission Control Protocol (TCP) header and data creating unit for creating data and a TCP header; a Media Access Control (MAC) header creating unit for creating an MAC header; a main control unit (MCU) for controlling header creation to transmit a packet; and a cache memory.

Apparatus and method for transmitting packet IP offload

Provided are a hardware device and a method for creating and managing socket information serving as a connection with a network protocol hierarchy in a network application program. The hardware device includes a TCP transmission processor for processing commands on requests for creating and eliminating a socket of a predetermined network program in response to the requests for creating and eliminating a socket, a TCP reception processor for creating a search signal for a corresponding socket identification when a new packet is received, a socket management unit for creating and eliminating a socket ID upon a command from the TCP transmission processor, and searching the socket ID and providing the socket ID to the TCP transmission processor upon a command from the TCP reception processor, and a memory unit for storing the socket information, and providing the socket information to the TCP reception processor.

Hardware device and method for creation and management of toe-based socket information

Provided are a microprocessor suitable for constructing a multi-processor system and a method for controlling the reset and processor ID of the microprocessor. The microprocessor includes decoder receiving a reset ID having a predetermined binary value and a reset signal and decoding the reset ID, an ID generator receiving the decoding result of the decoder and generating at least one microprocessor ID and a reset ID of a microprocessor serially connected to the microprocessor, and a reset vector unit selecting a reset vector according to the decoding result of the decoder. The multi-processor system is constructed such that independent microprocessors of the system respectively generate their own reset vectors and processor IDs when a reset signal is input to the multi-processor system to initialize it. Thus, all the microprocessors of the system can be simultaneously started up when the reset signal is disabled. Accordingly, a resetting process in the multi-processor system is simplified, a period of time required for starting up the microprocessor is reduced, and the multi-processor system is easily designed.

Multi-processor system and method for controlling reset and processor ID thereof

A radio frequency identification (RFID) tag based object position tracking apparatus and method are provided. The apparatus includes a position recognizer including at least one radio frequency identification unit for reading information data on an object through a sensor; and a path analyzing and processing unit for allocating each unique coordinates to the radio frequency identification units based on a relative position in a space where a position recognizer is disposed and recognizing the position of the object and analyzing the path based on the object information data received by the sensor in the radio frequency identification unit corresponding to the unique coordinate. Thus, it is possible to track the path of an object with a low density of RFID tags.

Apparatus for identifying objects using radio frequency and apparatus and method for tracking position of object using the same

A method for converting an IBIS (Input/output Buffer Information Specification) model to a SPICE (Simulation Program with Integrated Circuit Emphasis) behavioral model by RC (resistor/capacitor) extraction is provided. In the method, when the SPICE behavioral models of pull-up and pull-down transistors being switching components of the output IBIS model is embodied, a resistance is extracted from voltage-current tables of the pull-up and pull-down transistors and a capacitance is extracted from voltage-time tables of the pull-up and pull-down transistors so that a static characteristic is modeled as a resistor and a dynamic characteristic is modeled as a capacitor.

Method for converting IBIS model to SPICE behavioral model by extracting resistor and capacitor

In a first-in first-out memory circuit using a standard cell library memory, a memory block includes N number of memories (N&#x3e;1). A read pointer designates read addresses of the N number of memories. A write pointer designates write addresses of the N number of memories. A memory controller selects one from the N number of memories based on the read/write addresses, generates n number of read/write clock signals by demultiplying a clock signal by n (n=N, n&#x3e;1) and sends the n number of read/write clock signals having a 1/n cycle difference to the N number of memories thereby inputting/outputting data.

First-in first-out memory circuit and method for executing same

Disclosed herein is an interrupt redirection apparatus and method for inter-processor communication. The apparatus includes a plurality of ARM processors, a vectored interrupt controller, an interrupt command register, an interrupt data register for designating the contents of each interrupt, an interrupt signal generation unit, and a bus interface unit used for providing read and write accesses of both the interrupt command register and the interrupt data register. The vectored interrupt controller for receiving interrupts generated by hardware for performing a specific function under the control of each ARM processor and interrupts generated by peripheral hardware, and transferring each interrupt as each interrupt request signal to an ARM processor designated as a master processor. The interrupt command register designates targets and kinds of each interrupt to perform a function for receiving an interrupt redirection command and activating an interrupt request signal. The interrupt signal generation unit reads the contents and activates an interrupt request signal.

Growing community of inventors

Daejeon, South Korea

Kyoung Ran Park