Samsung Electronics Co., Ltd.

Kyoung-Park Kim

Sung-Ho Ryu

Min-Soo Lim

An apparatus may include a first phase control circuit and/or a second phase control circuit. The first phase control circuit may compare the phase of the first clock signal with the phase of the second clock signal, and may control the phase of the first clock signal based on the result of the comparison. The second phase control circuit may control the phase of the second clock signal based on the result of the comparison output from the first phase control circuit. The first phase control circuit may control the phase of the first clock signal and/or the second phase control circuit may control the phase of the second clock signal such that they are synchronized with each other.

Systems, apparatuses and methods for synchronizing clock signals

A memory controller and a semiconductor device comprising the same are provided. The semiconductor device comprises a memory block comprising a plurality of memory banks and a memory controller. The memory controller outputs an auto refresh command and memory bank information indicating a memory bank that is to be auto refreshed in an auto refresh mode. Thus, only the selected memory bank performs an auto refresh operation in the auto refresh mode while reducing current consumption in the semiconductor device.

Memory controller and semiconductor comprising the same

A slave device may be configured to receive at least one bus interface clock and bus interface signals from a bus coupled to the at least one bus interface unit. The slave device may also be configured to operate independently of at least one main function clock.

Slave devices and methods for operating the same

A delay signal generator circuit is provided. A delay circuit including a plurality of series-connected inverters for sequentially delaying a first clock signal and for generating a plurality of delay signals and a multiplexer for selecting one of the delay signals. A delay control circuit samples the selected delay signal in response to a transition of a second clock signal. The second clock signal has twice the frequency of the first clock signal, and the delay control circuit controls the delay circuit based upon the sampled value(s) so that the selected delay signal output from the delay circuit has a delay time of &#xbc; clock cycle relative to the first clock signal.

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Suwon-si, South Korea

Kyoung-Park Kim