Samsung Electronics Co., Ltd.

Kyoung-mo Yang

Sang-Kil Lee

Bo-un Yoon

Sang-rok Hah

Jae-Dong Lee

Byung-am Lee

A method of controlling a wafer polishing time using a sample-skip algorithm and a method of polishing a wafer using the same are provided. According to the method of controlling a wafer polishing time, a chemical mechanical polishing (CMP) process is performed on a plurality of wafers of an n-th lot among a plurality of lots, each lot consisting of a plurality of wafers, for a time &Dgr;t(n), to calculate the amount removed &Dgr;ToxP(n) from a polished layer on the wafer. The removal rate RR (n) of a layer on a blanket wafer is calculated from the amount removed &Dgr;ToxP(n). A CMP time &Dgr;t(n&plus;1) is determined for wafers of an n&plus;1-th lot using the relationship equation &Dgr;t(n&plus;1)&equals;&lcub;&Dgr;ToxT(n&plus;1)&plus;A&rcub;/RR (n) where &ldquo;A&rdquo; is a constant and &Dgr;ToxT(n&plus;1) is the target amount of a layer to be removed from a wafer of an n&plus;1-th lot.

Method of controlling wafer polishing time using sample-skip algorithm and wafer polishing using the same

A submicron level dimension reference for use with a scanning electron microscope in a semiconductor device fabrication apparatus. The reference has a first insulating layer with a first pattern formed on a semiconductor wafer substrate. A plurality of contacts are formed between the first pattern of the first insulating layer such that the contacts directly communicate the wafer substrate. The contacts are capable of carrying an electrical charge. An electrically conductive layer is formed over the contacts and the first insulating layer. A second insulating layer with a second pattern is formed over the conductive layer. Electrical charges generated by radiating the scanning electron microscope on the submicron level dimension reference are transferred from the first and second insulating layers to the wafer substrate via the conductive layer and the plurality of contacts.

Using a submicron level dimension reference

A method for testing a contact opening of a semiconductor device includes the steps of: inspecting a wafer using an in-line scanning electron microscope, comparing a contrast difference of contact opening regions displayed on the scanning electron microscope, and determining whether the processes for forming the contact openings have been performed correctly based on results of the comparison step. The test method may be performed after any of a contact photolithography process, contact etching process, or conductive layer etching process.

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Suwon, South Korea

Kyoung-mo Yang