Samsung Electronics Co., Ltd.

Kyoung Lae Cho

Jun Jin Kong

Jae Hong Kim

Seung-Hwan Song

Yong June Kim

Dong Hyuk Chae

Heeseok Eun

Young Hwan Lee

Jong Han Kim

Sung-Jae Byun

Sung Chung Park

Yoon Sun Park

Hong Rak Son

Yoon Dong Park

Nam Phil Jo

Donghun Yu

Jaehong Kim

Seung Jae Lee

Junjin Kong

Seung Hoon Lee

Kwang Soo Seol

Dong Ku Kang

Chan Ho Yoon

Jae-Hong Kim

Pil Sang Yoon

Beom Kyu Shin

Jong Seon No

Dong Hun Yu

Sung Ii Park

Jae Dong Yang

Seok Il Youn

Eric R Fossum

Hyun Min Cho

Tae Hun Kim

Seok Lee

Dongku Kang

Sang Hoon Lee

Young Gu Jin

Sung-Il Park

Kwang Ho Kim

Dong Ki Min

Young Gyu Kang

In-sung Joe

In Sung Joe

Chanho Yoon

Ki Jun Lee

Sung Ho Seo

Jung Pil Lee

Kyung Phil Yoo

Hyuck-Sun Kwon

Seong Hyeog Choi

Myung Sub Shin

Hee Seok Eun

Hee Chang Cho

Bumseok Yu

Ju Hee Park

Jin Hyeok Choi

Seong Sik Hwang

Jung Hun Sung

Ha Bong Chung

Keun Sung Choi

An embedded multimedia card (eMMC) is provided. The eMMC includes a clock channel receiving a clock output from a host, data channels receiving data signals from the host, and a command channel receiving a SWITCH command including delay offset values from the host so as to adjust a delay of at least one of the data signals, which are received, in response to the delay offset values.

Embedded multimedia card (eMMC), host controlling eMMC, and method operating eMMC system including the use of a switch command defining an adjustment delay for a data signal

A method of operating a data compression device includes analyzing data using an analyzer and generating a result of the analysis, while the data is buffered by an input buffer, and selectively compressing the buffered data according to the result of the analysis. A data compression device includes a data pattern analyzer configured to analyze data transmitted to an input buffer, and generate an analysis code based on the analysis of the data; and a data compression manager configured to selectively compress the data in the input buffer based on the analysis code.

Data compression devices, operating methods thereof, and data processing apparatuses including the same

A memory system including a non-volatile memory device and a memory controller is provided. When a read operation on a first data initially output from the non-volatile memory device during a first read operation is successful, the memory controller may change a read voltage for reading a second data stored in the non-volatile memory device during a second read operation.

Method for changing read parameter for improving read performance and apparatuses using the same

Memory devices and/or methods of managing memory data errors are provided. A memory device detects and corrects an error bit of data read from a plurality of memory cells, and identifies a memory cell storing the detected error bit. The memory device assigns a verification voltage to each of the plurality of first memory cells, the assigned verification voltage corresponding to the corrected bit for the identified memory cell, the assigned verification voltage corresponding to the read data for the remaining memory cells. The memory device readjusts the data stored in the plurality of memory cells using the assigned verification voltage. Through this, it is possible to increase a retention period of the data of the memory device.

Memory device and method of managing memory data error including determining verification voltages and changing threshold voltages based on a corrected error bit

A method of programming a non-volatile memory device including a plurality of strings arranged in rows and columns comprises activating all or a part of selection lines in one column at the same time depending upon data to be programmed, driving a bit line corresponding to the one column with a bit line program voltage, and repeating the activating and the driving until bit lines corresponding to the columns are all driven.

Non-volatile memory device capable of multi-page programming by simultaneously activating a plurality of selection lines based on programmed data

A data storage device includes a non-volatile memory device including a plurality of memory cells and a memory controller. The memory controller is configured to modify an arrangement of program data and to program the modified program data into the plurality of memory cells. The memory controller modifies the program data to eliminate a given data pattern causing physical interference between adjacent memory cells from the modified program data.

Data storage device and program method that modifies arrangement of program data to eliminate interfering data patterns

A non-volatile semiconductor memory device and related method of determining a read voltage are disclosed. The non-volatile semiconductor memory device includes; a memory cell array including a plurality of memory cells, a read voltage determination unit configured to determine an optimal read voltage by comparing reference data obtained during a program operation with comparative data obtained during a subsequent read operation and changing a current read voltage to a new read voltage based on a result of the comparison, and a read voltage generation unit configured to generate the new read voltage in response to a read voltage control signal provided by the read voltage determination unit.

Non-volatile memory device, memory card and system, and method determining read voltage by comparing referenced program data with comparative read data

A method of storing data in a storage media can include determining whether a size of data to be stored in the storage media satisfies a reference condition and compressing the data to provide compressed data for storage in the storage media upon determining that the size satisfies a reference condition.

Method, device and system for storing data in storage media using a reference condition

Method for multi-page programming a non-volatile memory device by simultaneously activating a plurality of selection lines based on programmed data

A method of storing data in a storage medium of a data storage device comprises storing input data in the storage medium, and reading the input data from the storage medium and compressing the read data during a background operation of the data storage device.

Data storage device and method performing background operation with selected data compression

A method of encoding multi-bit level data includes: determining a range of an error pattern generated according to a transmission symbol, encoding an M-bit level of a P-bit level corresponding to the transmission symbol based on the range of the error pattern, and excluding encoding of a P-M bit level of the P-bit level. The variable P is a natural number of a value at least two, and the variable M is a natural number less than P.

Method of encoding and decoding multi-bit level data

An iterative decoding method is disclosed and includes sequentially executing a number of iterative decoding cycles in relation to a parity check equation until the parity check equation is resolved, or a maximum number N of iterative decoding cycles is reached, during execution of the number of iterative decoding cycles, storing in a data buffer minimum estimated values for a set of variable nodes corresponding to a minimum number of bit errors, and outputting the minimum estimated values stored in the data buffer as a final decoding result when the number of iterative decoding cycles reaches N.

Iterative decoding method and apparatus

An error correction apparatus, a method thereof, and a memory device including the apparatus are provided. The error correction apparatus may include: a determination unit configured to determine whether a number of errors in a read word being read and extracted from a multi-level cell (MLC) exists in an error correcting capability range; a read voltage control unit configured to either increase or decrease a read voltage applied to the MLC when the number of errors in the read word is outside the error correcting capability range; and a codeword determination unit configured to analyze a bit error based on the increase or decrease of the read voltage, and to select a codeword corresponding to the analyzed bit error based on a selected read error pattern. Through this, it may be possible to efficiently correct a read error that occurs when the data of the memory device is maintained for a long time.

Apparatus, method and memory device for error correction by increasing or decreasing a read voltage and analyzing frequency information for a read error pattern

A method of reading data in a non-volatile memory device. The method includes reading a plurality of memory cells of a first page in a memory cell array using a first read level, reading a plurality of memory cells of a second page adjacent to the memory cells of the first page using a second read level, determining whether a state of each memory cell of the first page has been changed based on the first read level to verify a threshold voltage of each memory cell of the second page based on the second read level, and revising the state of each memory cell of the second page according to a result of the determination.

Method of reading data in non-volatile memory device, and device thereof

Growing community of inventors

Yongin-si, South Korea

Kyoung Lae Cho