Samsung Electronics Co., Ltd.

Kyoung June Min

Seok Yoon Jung

Chan Min Park

Hee Seok Kim

Sang Oak Woo

Suk Jin Kim

Jong Myon Kim

Soojung Ryu

Dong-hoon Yoo

Won Jong Lee

Kwon Taek Kwon

Jeongwook Kim

Sung Jin Son

Jeong Wook Kim

Jun Jin Kong

Dong-Hoon Yoo

Hong-Seok Kim

Dong Soo Kang

Dong Kwan Suh

Yeon Gon Cho

Myon Jong Kim

Disclosed are a reconfigurable processor and processing method, a reconfiguration control apparatus and method, and a thread modeler and modeling method. A memory area of a reconfigurable processor may be divided into a plurality of areas, and a context enabling a thread process may be stored in respective divided areas, in advance. Accordingly, when a context switching is performed from one thread to another thread, the other thread may be executed by using information stored in an area corresponding to the other thread.

Reconfigurable processor and method

A tile-based rendering apparatus and method is provided. Vertex data sorted based on a tile unit may be stored in a scene buffer and be rendered. Among the stored vertex data, vertex data used several times for rendering may be temporarily stored in a memory or a cache. Vertex data having a probability of being read several times from the scene buffer may be temporarily stored in another memory.

Apparatus and method for tile-based rendering

A system and method of rendering three-dimensional (3D) graphics. The system for rendering 3D graphics may include a plurality of cores including a scratch pad memory, a first memory to perform a control flow, a second memory for loop acceleration, and a shared memory to interpolate with the plurality of cores.

System and method of rendering 3D graphics

A method and apparatus for processing a vertex may fetch pieces of position information of vertexes, may extract pieces of target position information from the fetched pieces of position information, may perform tile binning on the pieces of target position information, may fetch pieces of attribute information having same indexes as the pieces of target position information, and may shade the fetched pieces of attribute information.

Method and apparatus for processing vertex

A method to discard pixels early includes a first early depth test maintaining a depth value on a pixel to be discarded by a discard instruction, and a second early depth test updating the depth value on a pixel not to be discarded by the discard instruction. Because of the first and second early depth tests, a number of pixels to be processed by a pixel shading process may be reduced.

Apparatus and method of early pixel discarding in graphic processing unit

A format conversion apparatus which converts image data of a band interleave format into image data of a band separate format is provided. The apparatus includes a memory which stores image data of a band interleave format; and a converting module which reads the memory by increasing a read address of the memory for each stride, and converts the image data of the band interleave format into image data of a band separate format.

Format conversion apparatus from band interleave format to band separate format

A tile binning method including: dividing a scene for rendering a triangle, into a plurality of tiles; determining identification values of tile nodes of each of the tiles; and identifying a tile including an entirety or a part of the triangle from the tiles, based on the identification value of the tile nodes for each of the tiles.

Method and system for tile binning using half-plane edge function

A method and system for an early Z test in a tile-based three-dimensional rendering is provided. In the method and system for an early Z test, a portion which is not displayed to a user is removed prior to performing a rasterization process, and thereby performing the 3D rendering efficiently. The method includes segmenting a scene into tiles for performing a rendering with respect to a triangle; selecting a first tile of the tiles, which has a tile Z value less than a minimum Z value of the triangle; and performing the rendering with respect to the triangle in remaining tiles excluding the selected first tile of the tiles.

Method and system for early Z test in title-based three-dimensional rendering

A processor and a memory controlling method. The processor enables a Scratch-Pad Memory (SPM) to prepare data that a processor core intends to process, using a data management unit including a data cache, thereby increasing a data processing rate.

Processor and method for controlling memory

A memory access method includes: obtaining a, b, and c from a program code for accessing a memory with a triple loop in a program, a being a number of values which an inner-most loop variable of the triple loop may have, b being a number of values which a middle loop variable of the triple loop may have, and c being a number of values which an outer-most loop variable of the triple loop may have; obtaining a starting address of the memory accessed by the triple loop; and obtaining an a&#xd7;b&#xd7;c number of addresses of the memory accessed by the triple loop using the starting address and a function.

Growing community of inventors

Yongin-si, South Korea

Kyoung June Min