Samsung Electronics Co., Ltd.

Skhynix Inc.

Kyoung-Hwan Kwon

Ho-Cheol Lee

Nam-Jong Kim

Hyong-Ryol Hwang

Hyo-Joo Ahn

Kyu-Hyoun Kim

Hyun-Soon Jang

Hyun-Sang Park

Choong-Bin Kim

Dong-Heon Han

Kwang-sook Noh

A display device includes at least one display panel and a display driver integrated circuit (DDI). The at least one display panel includes a first display region and a second display region. The DDI includes a first timing controller-embedded driver (TED) and a second TED. The first TED is configured to process a first image data to provide a first display data to the first display region and the second TED is configured to process a second image data to provide a second display data to the second display region. The first TED is configured to control display timings of the first display data and the second display data.

Display driver integrated circuit including a plurality of timing controller-embedded drivers for driving a plurality of display regions in synchronization and a display device including the same

A data input circuit includes a valid strobe signal generation circuit and a data strobe signal counter. The valid strobe signal generation circuit is configured to remove a pulse of an internal strobe signal generated and generate a valid strobe signal. The pulse may have been generated during a preamble period. The data strobe signal counter is configured to count the valid strobe signal according to burst length information and generate a write latch signal for aligning data at a time of a write operation.

Data input circuit with a valid strobe signal generation circuit

A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.

Multi-port semiconductor memory device having variable access paths and method therefor

A multi-port semiconductor memory device having variable access paths and a method therefore are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.

Multi-port semiconductor memory device having variable access paths and method

In a frequency multiplier and a method of multiplying a frequency of an external clock signal, a data output buffer, and a semiconductor device including the frequency multiplier and the data output buffer, the frequency multiplier receives an external clock signal having a predetermined frequency and outputs an internal clock signal having greater frequency than the predetermined frequency. In the semiconductor device, the data output buffer outputs data tested in response to test data. Therefore, it is possible to test a plurality of memory cells at a time by using a clock signal having a low frequency. In addition, the time and cost required for the test can be greatly reduced, and conventional testing equipment that operates at a relatively low frequency can be effectively used.

Semiconductor device comprising frequency multiplier of external clock and output buffer of test data and semiconductor test method

Provided are an integrated circuit and a method thereof, in which different types of signals can be applied to an internal circuit via one pin. The integrated circuit device includes a distribution unit, a level fixing unit, and an activation unit. The distribution unit receives and outputs a first input signal input via the first input pin, and receives and outputs a second input signal input via the first input pin in response to a control signal. The level fixing unit receives the first input signal from the distribution unit and applies a signal having the same voltage level as the first input signal to a first internal circuit in response to the control signal. The activation unit receives the second input signal input via the second input pin and then applies the second input signal to a second internal circuit or applies the second input signal output from the distribution unit to the second internal circuit in response to the control signal.

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Seoul, South Korea

Kyoung-Hwan Kwon