Korea Advanced Institute of Science and Technology

Kyoung Hoon Yang

Tae Ho Kim

Young Se Kwon

Sun Kyu Choi

Myoung Hoon Yoon

Moon Jung Kim

Ha Joon Lee

Soo Kun Jeon

Disclosed herein is a multiplexer circuit. The multiplexer circuit includes a first differential output unit, a second differential output unit, and a selection unit. The first differential output unit receives NRZ input signals (Dand) and a clock signal (CLK), and generates differential RZ-mode outputs (Rand). The second differential output unit receives NRZ input signals (Dand) and an inverted clock signal (), and generates differential RZ-mode outputs (Rand). The selection unit receives the RZ-mode output signals (R,, R, and) generated at the first differential output unit and the second differential output unit, and generates NRZ mode outputs in each half cycle of the clock signal (CLK).

Multiplexer circuit

Disclosed herein is an active pixel sensor having a first transistor amplifying voltage generated in response to light at an integration node; a second transistor selects a specific pixel from a pixel array; a third transistor resets voltage of the integration node to voltage supplied from VDD during a reset period; a fourth transistor connects a photogate capacitance to the integration node increasing a dynamic range when the voltage of the integration node is VDD-Vth; a fifth transistor generates a signal voltage in a logarithmic response to light when the voltage of the integration node is logarithmic bias voltage-Vth; and a photodiode to convert photons into electron pairs in a depletion layer, causing signal charges to be accumulated when light is incident from outside.

Pixel sensors using nonlinear capacitance with logarithmic characteristics

The present invention relates to CML(Current Mode Logic)-type input driving method and tunneling diode logic using MOBILE(Monostable Nistable transition Logic Element) configuration, as kinds of very high-speed digital logic circuits. The objectives of the present invention are to improve the disadvantage of MOBILE circuit configuration that is an existing tunneling diode logic, and at the same time provide new MOBILE based logic functions. Wherein, the difficulty for input voltage adjustment is resolved by replacing the input part with a CML input driving gate, and speed problem due to transistor is resolved. Moreover, a plurality of logic functions such as inverted return-to-zero D flip-flop, non-inverted return-to-zero D flip-flop, return-to-zero OR gate, return-to-zero D flip-flop generating differential output, and optical flip-flop are implemented.

Tunneling diode logic IC using CML-type input driving circuit configuration and monostable bistable transition logic element (MOBILE)

Method of reducing device parasitic capacitance using underneath crystallographically selective wet etching

Disclosed is a method for fabricating a self-aligned submicron gate electrode using an anisotropic etching process. The method involves the steps of laminating a dummy emitter defining a dummy emitter region over a heterojunction bipolar transistor structure including layers sequentially formed over a semiconductor substrate to define a base region, an emitter region, and an emitter cap region, respectively, defining a line having a width of about 1 micron on the dummy emitter by use of a photoresist while using a contact aligner, selectively anisotropic etching the dummy emitter at a region where the line is defined, to allow the dummy emitter to have an etched portion having a bottom surface with a width less than the width of the line defined by the photoresist, and depositing a contact metal on the etched portion of the dummy emitter, thereby forming a gate. In accordance with the present invention, a reliable submicron gate can be fabricated using a simple anisotropic wet etch process and an inexpensive contact aligner. Accordingly, the manufacturing costs can be reduced. In the formation of a base electrode involved in the fabrication of an HBT device, the present invention also provides an effect of reducing the distance between a base and an emitter, thereby achieving a reduction in base resistance, by virtue of a self-alignment using a V-shaped submicron gate.

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Daejon, South Korea

Kyoung Hoon Yang