Samsung Electronics Co., Ltd.

Kyoung-Hoon Kim

Dae-Hun Jung

Yeon-moo Chung

Yun-Je Kang

Jin-Su Park

Sin-Wi Moon

Hoosung Cho

Hong-soo Kim

Woo-Kwang Lee

Hansoo Kim

Jaehoon Jang

Ji-gwang Kim

Sung-Il Bang

Taehee Lee

Jun-Ho Yang

Young-Sun Shin

Tae-Yeon Won

Jaehun Jeong

Hongsoo Kim

Dan-Bi Kang

Dong-Rak Shin

Sung-Min Hwang

Wonseok Cho

Min-Hee Lee

Jong-Seok Kim

Jae-Joo Shim

Jae-Beom Park

Koung-Won Park

Sangyoun Jo

Tae-hee Lee

Woo-Sung Yang

One-Gun Lee

Ju-Yeon Lee

Hee-Sung Kam

Jin-Woo Park

Sang-Il Park

Dae-Hyun Kim

Joon-soo Kim

Ju-won Cho

Seok-Jun Won

Hyuk Kang

Tae-Hee Lee

Gyoo-Sang Choi

Byoungkeun Son

Hyun-Jung Kim

Young-wook Park

Suk-jin Kim

Dae-hyun Kim

Je-Kook Kim

Jintaek Park

Seok-Won Lee

Woonkyung Lee

Jae-Hyun Ahn

Sung-Eun Lee

Baek-Ki Kim

Jong-Man Park

Yu-Dong Bae

Kyung-Won Park

Young-Hwan Park

Seungwoo Paek

Jeong-Hun Seo

Guneet Singh Khurana

Kab-jin Nam

Jong-Yeon Kim

Joon-Yung Park

Kyoung-Won Kim

Dong-Kwan Suh

Keshava Prasad Nagaraja

Keshava Prasad

Jee-hoon Hwang

Sunyeong Lee

Ho-Sun Lee

Taekeun Cho

Young-suk Lee

Kang-Jun Ko

Suk-Jin Kim

Bon-Seuk Goo

Sun-woo Kwak

Duk-soo Yoon

Jong-Ik Won

In-Geol Lee

Hyoung-Woo Jang

Min-Gi Kim

Han-Su Cho

An electronic device and a method for sensing moisture in an electronic device are provided. The method for sensing moisture in an electronic device includes sensing moisture introduced into a connector of the electronic device in a state where one or more functions executable by connection of the connector with an external electronic device are activated. Further, the method includes deactivating the one or more functions based on the sensing; determining whether the introduced moisture is removed in a state where the one or more functions are deactivated; and activating the one or more functions if the moisture is removed.

Electronic device and method for sensing moisture in an electronic device

A vertical memory device includes a substrate including a cell region and a peripheral circuit region, gate electrodes sequentially stacked on the cell region of the substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel on the cell region and extending through the gate electrodes in the vertical direction, a first lower contact plug on the peripheral circuit region and extending in the vertical direction, a second lower contact plug on the peripheral circuit region adjacent to the first lower contact plug and extending in the vertical direction, and a first upper wiring electrically connected to the first lower contact plug. The first upper wiring is configured to and apply an electrical signal to the first lower contact plug. The second lower contact plug is not electrically connected to an upper wiring configured to apply an electrical signal.

Vertical memory devices

Electronic devices according to various embodiments of the present invention comprise: a connector for communicating serial data to an external electronic device; a nonvolatile memory; and a processor, wherein the processor is configured to: acquire identification information of the external electronic device via the connector; confirm whether or not a designated mode of the external electronic device is supported at least on the basis of the identification information; based on the identification that the external electronic device supports the designated mode, acquire first additional information associated with the external electronic device; based on the identification that the external electronic device does not support the designated mode, acquire second additional information associated with the external electronic device; and store the identification information or at least a part of the second additional information in the nonvolatile memory.

Electronic device and method for controlling same

A semiconductor device includes a substrate including a resistor region, a plurality of lower patterns in the resistor region, and a resistor line pattern on the plurality of lower patterns and the substrate of the resistor region. The plurality of lower patterns extend in a first direction parallel to a surface of the substrate and are spaced apart from each other in a second direction perpendicular to the first direction and parallel to the surface of the substrate. The resistor line pattern extends in the second direction. The resistor line pattern on the lower patterns has an upper surface and a lower surface protruding in a third direction perpendicular to the surface of the substrate.

Semiconductor device including resistor structure

Provided is a three-dimensional semiconductor memory device. The device may include a substrate that includes a cell array region and a connection region; an electrode structure provided on the substrate to extend in a first direction and include electrodes that are vertically stacked on the substrate and include pad portions which are stacked on the connection region to have a staircase structure; cell vertical structures provided on the cell array region to penetrate the electrode structure; dummy vertical structures provided on the connection region to penetrate the pad portion of each electrode; and cell contact plugs coupled to the pad portions of the electrodes. Each cell contact plug may have a non-circular top surface, and the dummy vertical structures may be arranged to surround each cell contact plug, in a plan view.

Three-dimensional semiconductor memory device

A vertical memory device includes a substrate with a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes parallel to the substrate in the cell array and word line contact regions, the gate electrodes being stacked and spaced apart in a direction perpendicular to the substrate, a channel structure through the gate electrodes in the cell array region, the channel structure being electrically connected to the substrate, a dummy channel structure through the gate electrodes in the word line contact region, the dummy channel structure being spaced apart from the substrate, and a conductive line parallel to the substrate and electrically connected to a first gate electrode, the conductive line crossing at least a portion of an extension of the dummy channel structure in the perpendicular direction.

Vertical memory device and method of fabricating the same

A vertical memory device includes a conductive pattern structure on a first region of a substrate, the conductive pattern structure including a stack of interleaved conductive patterns and insulation layers. A pad structure is disposed on a second region of the substrate adjacent the first region of the substrate wherein edges of the conductive patterns are disposed at spaced apart points along a first direction to provide conductive pads arranged as respective steps in a staircase arrangement. A plurality of channel structures extends through the conductive pattern structure and a plurality of dummy channel structures extends through the pad structure. Respective contact plugs are disposed on the conductive pads. Numbers of the dummy channel structures per unit area passing through the conductive pads vary. Widths of the dummy channel structures passing through the conductive pads may also vary.

Vertical memory devices with conductive pads supported by dummy channels with varying dimensions

A semiconductor device includes a plurality of line patterns formed apart from one another on a substrate, the plurality of line patterns having a first width and extending parallel to one another in a first direction. A first line pattern of the plurality of line patterns may include a wider portion having a second width in a second direction perpendicular to the first direction that is greater than the first width. One or more second line patterns may be located adjacent to the first line pattern and include a conformal portion conformally formed about the wider portion of the first line pattern. One or more third line patterns may be located adjacent to the second line pattern and include an end portion near the conformal portion of the one or more second line pattern.

Semiconductor device and method of manufacturing a semiconductor device

A method of operating an electronic device is provided. The method includes communicating data with a wireless network using a wireless communication, connecting to an external electronic device using a wired communication, exchanging data with the external device at a first data throughput using the wired communication while performing the wireless communication, and changing the first data throughput to a second data throughput while performing the wireless communication.

Method for controlling transmission speed and electronic device thereof

A three-dimensional (3D) semiconductor memory device may include a substrate including a cell array region and a connection region, an electrode structure including pluralities of first and second electrodes that are vertically and alternately stacked on a surface of the substrate, extending in a first direction that is parallel to the surface of the substrate, and may include a stair step structure on the connection region, first and second string selection electrodes that extend in the first direction on the electrode structure and spaced apart from each other in a second direction that is parallel to the surface of the substrate and perpendicular to the first direction. The first and second string selection electrodes may each include an electrode portion on the cell array region and a pad portion that extends from the electrode portion in the first direction and on the connection region. Widths in the second direction of the pad portions may be different from widths in the second direction of the respective electrode portions.

Three-dimensional (3D) semiconductor memory devices

A highly integrated semiconductor memory device includes a substrate, a plurality of vertical pillars above the substrate, a plurality of connection lines extending over the vertical pillars, a plurality of lower via plugs provided above the vertical pillars and connecting the vertical pillars to the connection lines, a dummy connection line provided at a same level as the connection lines with respect to a main surface of the substrate, and a dummy via plug connected to a lower surface of the dummy connection line and having a different height than each of the lower via plugs. The vertical pillars, the connection lines, the lower via plugs are provided in a cell region, and the dummy connection line and the dummy via plug are provided in a dummy region.

Semiconductor memory device

A semiconductor memory device may include an electrode structure including a selection line on a substrate and word lines between the substrate and the selection line, vertical pillars penetrating the electrode structure and being connected to the substrate, sub-interconnections and bit lines sequentially stacked on and electrically connected to the vertical pillars, and lower contacts connecting the vertical pillars to the sub-interconnections. The selection line may include a plurality of selection lines separated from each other in a first direction by an insulating separation layer, and central axes of the lower contacts connected in common to one of the sub-interconnections may be shifted, in a second direction across the first direction and parallel to a top surface of the substrate, from central axes of the vertical pillars thereunder.

Semiconductor memory devices having vertical pillars that are electrically connected to lower contacts

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Seoul, South Korea

Kyoung-Hoon Kim