Samsung Electronics Co., Ltd.

Kyoung-Ho Jung

Dongjin Lee

Satoru Yamada

Moonyoung Jeong

Sungjin Kim

Ji Eun Lee

Han Jin Lim

Sung Heo

Jiho Yoo

Eunae Cho

Gyeongsu Park

Yongsu Kim

Dong Su Ko

Makoto Yoshida

Chul Ho Lee

Jae-Rok Kahng

Hyun Uk Park

Keun-Nam Kim

Ji-eun Lee

Hui-Jung Kim

Hyun Soo Park

Hyun Wook Park

Sung-Il Cho

Se-Myeong Jang

Joon-Seok Moon

Cheol-Kyu Lee

Hyun-Ju Sung

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate including a trench. The semiconductor device further includes a gate electrode disposed in the trench, and a gate insulating film disposed between the substrate and the gate electrode. The gate electrode includes a gate conductor and a metal element, and an effective work function of the gate electrode is less than an effective work function of the gate conductor.

Semiconductor device and method of manufacturing the same

Provided are a semiconductor device having a gate and a method of forming the same. The method includes forming a gate dielectric, forming a first conductive material layer on the gate dielectric, forming a source material layer on the first conductive material layer, and diffusing a first element included in the source material layer into the first conductive material layer by performing a thermal treatment process to form a doped material layer.

Semiconductor device having a gate and method of forming the same

A method of fabricating a semiconductor device for reducing a thermal burden on impurity regions of a peripheral circuit region includes preparing a substrate including a cell active region in a cell array region and peripheral active regions in a peripheral circuit region. A cell gate pattern and peripheral gate patterns may be formed on the cell active region and the peripheral active regions. First cell impurity regions may be formed in the cell active region. A first insulating layer and a sacrificial insulating layer may be formed to surround the cell gate pattern and the peripheral gate patterns. Cell conductive pads may be formed in the first insulating layer to electrically connect the first cell impurity regions. The sacrificial insulating layer may be removed adjacent to the peripheral gate patterns. First and second peripheral impurity regions may be sequentially formed in the peripheral active regions adjacent to the peripheral gate patterns.

Method of fabricating semiconductor device for reducing thermal burden on impurity regions of peripheral circuit region

For fabricating multiple field effect transistors (FETs), a first conductive layer is deposited over first and second active regions of a semiconductor substrate. The first conductive layer is patterned over the second active region to form mold structures. Mask structures are formed between the mold structures. The second active region is patterned using the mask structures or using spacers formed at sidewalls of the mold structures to form multiple fins of a field effect transistor of a fin type. The first conductive layer is patterned over the first active region to form a gate of another field effect transistor of a different type.

Method for fabricating multiple FETs of different types

A semiconductor device including an active pattern having a channel recess portion, and a method of fabricating the same, are disclosed. In one embodiment, the semiconductor device includes an active pattern including first active regions and a second active region interposed between the first active regions. The active pattern protrudes above a surface of a semiconductor substrate and includes a channel recess portion above the second active region and between the first active regions. A device isolation layer surrounds the active pattern and has a groove exposing side walls of the recessed second active region. A distance between opposing side walls of the first active regions exposed by the channel recess portion is greater than a distance between side walls of the groove. A gate pattern is located in the channel recess portion and extends along the groove.

Semiconductor device including active pattern with channel recess, and method of fabricating the same

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Suwon-si, South Korea

Kyoung-Ho Jung