Panasonic Corporation

Kyouji Yamashita

Daisaku Ikoma

Gaku Suzuki

Tomoyuki Ishizu

Masayuki Kamei

The present disclosure provides a method of performing circuit simulation of electrical characteristics of a transistor formed on a semiconductor substrate using calculators, each of which includes a memory. A first calculator receives mask layout data and distance-dependent data indicating a distance from the target transistor. Then, a second calculator calculates an area ratio of a layout pattern of a predetermined mask from the received mask layout data, and calculates a parameter &#x3b1; based on the area ratio and the distance-dependent data. Then, the second calculator B calculates a change &#x394;P in the electrical characteristics of the transistor based on the parameter &#x3b1;. This configuration provides highly accurate circuit simulation of the electrical characteristics of the transistor, which depend on variations in temperature distribution of the semiconductor substrate during heat treatment due to the mask layout pattern around the transistor.

Circuit simulation method and semiconductor integrated circuit

A semiconductor device includes a gate insulating film formed on a semiconductor region of a first conductivity type; a gate electrode formed on the gate insulating film; an offset spacer formed on a side surface of the gate electrode; an inner sidewall formed on the side surface of the gate electrode with the offset spacer interposed therebetween, and having an L-shaped cross section; and an insulating film formed to cover the gate electrode, the offset spacer, the inner sidewall, and a part of the semiconductor region located laterally outward from the inner sidewall. The offset spacer includes an inner offset spacer formed on the side surface of the gate electrode and an outer offset spacer formed to cover the side surface of the gate electrode and the inner offset spacer. The outer offset spacer is in contact with a top end and outer side surface of the inner offset spacer.

Semiconductor device and method for fabricating the same

A semiconductor device includes a first well region; a second well region; a first active regionsurrounded by an isolation region; a second active regionsurrounded by the isolation regionsandB; a first MIS transistor MPof a second conductivity type formed on the first active region; and including a source/drain region formed of a Si mixed crystal layer buried in a recess; a second MIS transistor MNof a first conductivity type formed on the second active region; and an isolation MIS transistor DPof the second conductivity type formed on the first active region. The source/drain region of the first MIS transistor is not in contact with the isolation regionlocated at an end of the first active regionin a gate length direction.

Growing community of inventors

Kyoto, Japan

Kyouji Yamashita