Samsung Electronics Co., Ltd.

Kyoo-chul Cho

Sam-jong Choi

Tae-soo Kang

Jea-gun Park

Gon-sub Lee

Young-Soo Park

Kyung-soo Kim

Jae-ryong Jung

Sang-Sig Kim

Shin-Hyeok Han

Yong-kwon Kim

Jung-Ho Lee

Youn-Joung Cho

Jung-Sik Choi

Jun-Hyun Cho

Seung-Min Ryu

Hee-Sung Kim

Gi-jung Kim

Gi-Jung Kim

Hoe-Sik Chung

Tae-Yeol Heo

Sung-hoon Cho

Ho-kyoon Chung

Yeon-Sook Kim

Jeong-hoon An

Jae-guen Park

Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

Integrated circuit device gate structures

Disclosed is a semiconductor wafer and method of fabricating the same. The semiconductor wafer is comprised of a semiconductor layer formed on an insulation layer on a base substrate. The semiconductor layer includes a surface region organized in a first crystallographic orientation, and another surface region organized in a second crystallographic orientation. The performance of a semiconductor device with unit elements that use charges, which are activated in high mobility to the crystallographic orientation, as carriers is enhanced. The semiconductor wafer is completed by forming the semiconductor layer with the second crystallographic orientation on the plane of the first crystallographic orientation, growing an epitaxial layer, forming the insulation layer on the epitaxial layer, and then bonding the insulation layer to the base substrate.

Semiconductor wafer and method of fabricating the same

Provided herein are methods of forming a metal oxide layer that include providing an organometallic compound and an oxidizing agent to the substrate to form the metal oxide layer on the substrate. The organometallic compound may have the general formula of M(NRR)R, wherein M is a metal; Rand Rare each independently hydrogen or alkyl; and Ris selected from the group consisting of alkyl, cycloalkyl, heterocycloalkyl, aryl and heteroaryl.

Methods of forming metal oxide layers, methods of forming gate structures using the same, and methods of forming capacitors using the same

Provided are a semiconductor device, and a method of forming the same. In one embodiment, the semiconductor device includes a semiconductor layer, first and second semiconductor fins, an insulating layer, and an inter-fin connection member. The first and second semiconductor fins are placed on the semiconductor layer, and have different crystal directions. The first semiconductor fin is connected to the semiconductor layer, and has the equivalent crystal direction as that of the semiconductor layer. The insulating layer is interposed between the second semiconductor fin and the semiconductor layer, and has an opening in which the first semiconductor fin is inserted. The inter-fin connection member connects the first semiconductor fin and the second semiconductor fin together on the insulating layer.

Semiconductor device and method for forming the same

Methods of forming integrated circuit device gate structures

A semiconductor wafer including an identification indication is provided. The wafer includes a convex edge with an upper surface area and a lower surface area. The identification indication is in a marking region which is disposed on a lower side surface of the convex edge. The lower side surface has a wide region where the marking region is located. This wide region has a width that is wider than an upper side surface of the wafer and thus makes a cross-section of a side of the wafer asymmetrical. With the present invention, the entire top surface of the semiconductor wafer can be utilized for a semiconductor chip region and prevents manufacturing problems associated with the uneven nature of the identification indication when the identification is located on the top surface of the wafer.

Semiconductor wafer having identification indication

Embodiments of the present invention provide methods for measuring a wafer surface. A portion of the wafer surface is measured using a particle counter to provide first measurements corresponding to a plurality of points on the wafer surface. A selected area of the wafer surface including one of the plurality of points is measured using an atomic force microscope (AFM) to provide a microroughness measurement of the selected area. The selected area is a localized area of the portion of the wafer surface measured using the particle counter. The first measurements and the microroughness measurement are provided as a measurement of the wafer surface. The portion measured using a particle counter may, for example, be substantially the entire wafer surface.

Methods and systems for measuring microroughness of a substrate combining particle counter and atomic force microscope measurements

A silicon ingot is manufactured in a hot zone furnace by pulling the ingot from a silicon melt in the hot zone furnace in an axial direction, at a pull rate profile of the ingot from the silicon melt in the hot zone furnace that is sufficiently high so as to prevent interstitial agglomerates but is sufficiently low so as to confine vacancy agglomerates to a vacancy rich region at the axis of the ingot. The ingot so pulled is sliced into a plurality of semi-pure wafers each having a vacancy rich region at the center thereof that includes vacancy agglomerates and a pure region between the vacancy rich region and the wafer edge that is free of vacancy agglomerates and interstitial agglomerates. According to another aspect of the present invention, the ingot is pulled from the silicon melt in the hot zone furnace at a pull rate profile of the ingot from the silicon melt in the hot zone furnace that is sufficiently high so as to prevent interstitial agglomerates, but is also sufficiently low as to prevent vacancy agglomerates. Accordingly, when this ingot is sliced into wafers, the wafers are pure silicon wafers that may include point defects but that are free of vacancy agglomerates and interstitial agglomerates.

Semi-pure and pure monocrystalline silicon ingots and wafers

A wafer packaging method in which a wafer is placed into a packaging bag that is sealed before the concentration of sulphuric oxide on the surface of the wafer reaches 3&times;10,atoms/cm,. The placing of the wafer in the wafer packaging bag is carried out in a substantially clean environment

Wafer packaging method

Methods of manufacturing monocrystalline silicon ingots and wafers by

With a view to optimizing the donor killing process performed in the semiconductor wafer fabricating process, a heat-treating operation is performed in a thermal furnace above at least 900 .degree. C. for a predetermined time so that growth of the initial oxygen precipitates, induced into the crystal lattices during single-crystal growth, is suppressed. Thus, the oxygen precipitates are easily suppressed, irrespective of the concentration of the initial oxygen, so that the yield of the semiconductor device is improved

Methods of heat-treating semiconductor wafers

Growing community of inventors

Gyeonggi-do, South Korea

Kyoo-chul Cho