Skhynix Inc.

Kyong Taek Lee

Sung Ho Kim

Min Sang Park

Gil Bok Choi

Yong Seok Suh

Sung Hoon Cho

Yun Bong Lee

Myoung Kwan Cho

Provided herein may be a semiconductor memory device that may include a plurality of memory blocks configured to share bit lines and a common source line, a voltage generation circuit configured to apply an erase voltage to the common source line, and operation voltages to word lines and select lines of the plurality of memory blocks during an erase operation, a read and write circuit configured to check a program and erase status of an unselected memory block of the plurality of memory blocks during the erase operation, and a control logic configured to control the voltage generation circuit so that the operation voltages applied to select lines of a selected memory block are controlled in accordance with a result of checking the program and erase status of the unselected memory block during the erase operation.

Control logic, semiconductor memory device, and operating method

A semiconductor memory device may include a control logic. The control logic may be coupled to bit lines through a read and write (read/write) circuit and to word lines. The control logic is configured to determine a duration of an activation time of a strobe signal for the read/write circuit.

Semiconductor memory device and operation method thereof

There are provided a semiconductor memory device and an operating method thereof. A semiconductor memory device may include a memory cell array, a peripheral circuit, a control logic, and one or more programs. The memory cell array may include a plurality of memory cells. The peripheral circuit may perform a program operation on the memory cell array. The control logic may control the peripheral circuit to program the memory cell array. The one or more programs are configured to be executed by the control logic. The programs may include an instruction for pre-programming one or more memory cells to be programmed to one or more target program states to have threshold voltage distributions lower than the target program state.

Semiconductor memory device including multi-level cell and programming method thereof

The semiconductor device includes a memory block including programmed pages and non-programmed pages, a peripheral circuit configured to perform a read operation of the memory block, and a control circuit configured to control the peripheral circuit so that a read voltage is applied to a word line coupled to a selected page among the pages for the read operation, a first pass voltage is applied to word lines coupled to the programmed pages among pages that are not selected for the read operation, and a second pass voltage lower than the first pass voltage is applied to word lines coupled to non-programmed pages among the pages that are not selected for the read operation.

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Yongin-si, South Korea

Kyong Taek Lee