Globalfoundries Singapore Pte. Ltd.

Kyong Jin Hwang

Jie Zeng

Robert J Gauthier, Jr

Prantik Mahajan

Milova Paul

Raunak Kumar

Sagar Premnath Karalkar

James Jerry Joseph

Aloysius Priartanto Herlambang

Robert John Gauthier, Jr

Elaine Xiao Mei Low

Ting Yang

The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge devices and methods of manufacture. The structure includes: a semiconductor material including an emitter region, a base region adjacent to the emitter region; and a collector region; a thermally grown insulator region on the semiconductor material extending from the base region to the collector region; and a field plate on the thermally grown insulator region and overlapping with the base region.

High-voltage electrostatic discharge device

Disclosed is a semiconductor structure including a device (e.g., a bi-directional semiconductor-controlled rectifier, such as a bi-directional silicon-controlled rectifier (BDSCR)) and, within the device, at least two dual-level isolation structures. Each dual-level isolation structure includes a first section at the top surface of the semiconductor substrate and one or more second sections extending through the first section deeper into the semiconductor substrate. The dual-level isolation structures are positioned within the device so as to increase well resistance. By increasing well resistance, the trigger voltage of the device can be reduced without increasing device size. Also disclosed is a method of forming dual-level isolation structures within such a device.

Bi-directional semiconductor-controlled rectifier with dual-level isolation structures and method

Structures for a high-voltage field-effect transistor that include a deep trench isolation region and methods of forming such structures. The structure comprises a semiconductor substrate, a semiconductor layer on the semiconductor substrate, and a doped layer between the semiconductor layer and the semiconductor substrate. The structure further comprises a trench isolation region including a metal layer that extends through the semiconductor layer and the doped layer into the semiconductor substrate.

Structures with deep trench isolation regions for a high-voltage field-effect transistor

The present disclosure relates to semiconductor structures and, more particularly, to improved turn-on voltage of high voltage electrostatic discharge device and methods of manufacture. The structure comprises a high voltage NPN with polysilicon material on an isolation structure located at a base region, the polysilicon material extending to at least one of a collector and emitter of a bipolar junction transistor (BJT), and the polysilicon material completely covering the base region of the BJT.

High voltage electrostatic devices

The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture. The structure comprising a vertical silicon controlled rectifier (SCR) connecting to an anode, and comprising a buried layer of a first dopant type in electrical contact with an underlying continuous layer of a second dopant type within a substrate.

High-voltage electrostatic discharge devices

The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture. The structure includes a vertical silicon-controlled rectifier (SCR) connecting to an anode, and includes a buried layer of a first dopant type in electrical contact with an underlying buried layer a second dopant type split with an isolation region of the first dopant type within a substrate.

An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a substrate, an active region, a first terminal region, and a second terminal region. The substrate includes dopants having a first dopant conductivity. The active region is arranged over the substrate and has an upper surface. The first terminal region and the second terminal region are arranged in the active region laterally spaced apart from each other. The first terminal region and the second terminal region each include a well region having dopants of the first dopant conductivity and a first doped region arranged in the well region. The first doped region includes dopants having a second dopant conductivity.

Electrostatic discharge protection devices for bi-directional current protection

A device includes a first region, a second region disposed on the first region, a third region and a fourth region abutting the third region disposed in the second region, a fifth region disposed in the third region and coupled to a collector disposed above, and a sixth region disposed in the fourth region and coupled to an emitter disposed above. A first isolation is disposed between the collector and the emitter. A seventh region is disposed in the fifth region and coupled to the collector is spaced apart from the first isolation. The first region, the third region, the fifth region, the collector and the emitter have a first conductivity type different from a second conductivity type that the second region, the fourth region, the sixth region and the seventh region have.

Device for electrostatic discharge protection

Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a structure for a laterally-diffused metal-oxide-semiconductor device. First and second source/drain regions are formed in a substrate, a gate electrode is formed over the substrate, an interconnect structure over the substrate, and a doped region is arranged in the substrate beneath the first source/drain region. The gate electrode is laterally positioned between the first and second source/drain regions, and the interconnect structure includes a contact connected to the first source/drain region. The doped region has a side edge that is laterally spaced from the contact by a distance.

Laterally-diffused metal-oxide-semiconductor devices for electrostatic discharge protection applications

A silicon controlled rectifier is provided. The silicon controlled rectifier comprises a substrate and a first n-well in the substrate. A p+ anode region may be arranged in the first n-well in the substrate. A first p-well may be arranged in the first n-well in the substrate. An n+ cathode region may be arranged in the first p-well in the substrate. A field oxide layer may be arranged over a first portion of the first p-well. A first gate electrode layer may extend over a second portion of the first p-well and over a portion of the field oxide layer.

Silicon controlled rectifier with a gate electrode for electrostatic discharge protection

An ESD protection device may include a substrate, a first conductivity region arranged at least partially within the substrate, a second conductivity region arranged at least partially within the first conductivity region, third and fourth conductivity regions arranged at least partially within the second conductivity region, and first and second terminal portions arranged at least partially within the third and fourth conductivity regions respectively. The third and fourth conductivity regions may be spaced apart from each other. The substrate and the second conductivity region may have a first conductivity type. The first conductivity region, third conductivity region, fourth conductivity region and first and second terminal portions may have a second conductivity type different from the first conductivity type. The first and second terminal portions may have higher doping concentrations than the third and fourth conductivity regions respectively.

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Singapore, Singapore

Kyong Jin Hwang