Panasonic Intellectual Property Management Co., Ltd.

Panasonic Corporation

Kyoko Ueda

Kenji Oga

Tadashi Yoshida

Daisuke Baba

Nobutaka Kitajima

Masakazu Nakazawa

Mutsumi Kawagoe

Yasuhiro Ito

Norifumi Murata

An anomaly detection method includes: reading a branch target address corresponding to a branch instruction, twice or more; determining whether the branch target addresses read are identical; and executing the branch instruction when the branch target addresses read are identical, and executing anomaly detection processing when the branch target addresses read are not identical.

Anomaly detection method, anomaly detection recording medium, anomaly detection device, rewriting method, and rewriting device

A safety confirmation support system includes: a moving object detector which detects a moving object in each of detection regions set around the vehicle; display units each associated with a different one of the detection regions; a line-of-sight detector which detects a line of sight of the driver; and a display controller which controls the display units based on detection results from the moving object detector and the line-of-sight detector. When the moving object is detected in a specified detection region, the display controller (i) displays moving object information on a specified display unit associated with the specified detection region when the line of sight is away from the specified detection region, and (ii) stops display of the moving object information on the specified display unit when the line of sight is towards the specified detection region while the moving object information is displayed on the specified display unit.

Safety confirmation support system and safety confirmation support method

Based on an input index sequence () composed of four indices (each having a bit width of 8 bits), a shift-copier generates an index sequence () by shifting each index leftward by 1 bit and making two copies of each index, and outputs the generated index sequence (). An adder generates a shuffle pattern () by adding 1, 0, 1, 0, 1, 0, 1 and 0 to the indices in the index sequence () from left to right, and outputs the generated shuffle pattern ().

Shuffle pattern generating circuit, processor, shuffle pattern generating method, and instruction sequence

When a temporary data storage unitstores a value of '3' and an iteration number of '3', and a data updating management unitreceives a value of &#x201c;2&#x201d; in combination with an iteration number of &#x201c;2&#x201d;, a data updating management unitdetermines not to overwrite information in the temporary data storage unitwith the received information by comparing the relative sizes of the iteration numbers. Subsequently, upon receiving information from the multithreaded execution unitindicating that parallel execution is complete, the data updating management unitcopies the value of &#x201c;3&#x201d;, stored by the temporary data storage unit, into the final data storage unit

Multithreaded parallel execution device, broadcast stream playback device, broadcast stream storage device, stored stream playback device, stored stream re-encoding device, integrated circuit, multithreaded parallel execution method, and multithreaded compiler

Growing community of inventors

Osaka, Japan

Kyoko Ueda