Fujitsu Corporation

Kyoko Tashima

Aiichiro Inoue

Masaki Ukai

Takeo Asakawa

An information processing apparatus is capable of speculatively performing an execution, such as a pipeline/superscalar/out-of-order execution and equipped with a branch prediction mechanism (a branch history). The information processing apparatus, in order to process an instruction sequence that includes a subroutine at a high speed, is further equipped with a return address stack, of which the stack operation is activated at a time of completing execution of an subroutine call/return correspondent instruction and an entry designating unit (pointer), in order to adjust a time difference resulting from an instruction fetch being executed prior to completing an instruction, pointing to a position relative to the stack front and adjusting a time difference between an instruction fetch performed speculatively in advance and completion of an instruction both at a time of completing execution of a branch instruction that is correspondent to a subroutine call/return and at a time of predicting a subroutine call/return in synchrony to the instruction fetch. An entry position correspondent to a stack position pointed to by the entry designation unit is adopted as a subroutine call/return prediction address and consequently the prediction of the subroutine return address becomes more accurate and the processing speed becomes higher.

Predicted return address from return stack entry designated by computation unit with multiple inputs including return hit flag and re-fetch signal

A pipeline process system, a super-scalar process system, or an out-of-order-execution process system is applied to an information processing device. A sequence of instructions containing a branch instruction, especially a subroutine, can be processed at a high speed using a branch history and a return address stack storing a return address corresponding to a subroutine call instruction. To successfully perform the process, when an instruction detected as a bit in the branch history is a subroutine return instruction, an address of a branched-to instruction registered in the branch history is compared with all return addresses stored in valid entries in the return address stack. A unit is provided to transmit a matching address as a return address of the return instruction to an instruction fetch unit for fetching an instruction.

Predicted return address selection upon matching target in branch history table with entries in return address stack

A general-purpose register address output from an instruction register is read and changed to a corresponding register update buffer address in an update table. Additionally, the update reservation instructing bit corresponding to the general-purpose register address is read out from a register update reservation table. If its value is '0', the general-purpose register address is provided to the general-purpose register, and the data stored at that address is input to an arithmetic unit. If the value of the bit is '1', the contents of the corresponding entry in the update table is registered to a reservation station. The reservation station determines the execution order of respective entries, and sequentially provides a register update buffer address to a register update buffer, and inputs the data stored at that address to the arithmetic unit.

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Kanagawa, Japan

Kyoko Tashima