Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Renesas Technology Corp.

Matsushita Electronics Corporation

Kyoji Yamashita

Takayuki Yamada

Mizuki Segawa

Takaaki Ukeda

Takashi Nakabayashi

Takashi Uehara

Toshiki Yabu

Masatoshi Arai

Daisaku Ikoma

Isao Miyanaga

Katsuhiro Ootani

Tatsuya Kunikiyo

Michikazu Matsumoto

Hiroyuki Umimoto

Tetsuya Watanabe

Shinji Odanaka

Katsumi Eikyu

Kazumi Kurimoto

Atsuhiro Kajiya

Toshiki Kanamoto

Yasuyuki Sahara

Mutsumi Kobayashi

Katsuhiro Ohtani

Atsushi Hori

Katsuya Arai

Yuka Terai

Akira Hiroki

Hiroaki Ishizuka

Tomoyuki Ishizu

Shinji Watanabe

Shinsaku Sekido

Katsuhiro Otani

Gate electrodesA throughF are formed to have the same geometry, and protruding parts of the gate electrodesA throughF extend across an isolation region onto impurity diffusion regions. The gate electrodeB and P-type impurity diffusion regionsBare connected through a shared contactAto a first-level interconnect MH, and the gate electrodeE and N-type impurity diffusion regionsAare connected through a shared contactAto a first-level interconnect MI. In this way, contact pad parts of the gate electrodesA throughF can be located apart from active regions of a substrate for MOS transistors. This suppresses the influence of the increased gate length due to hammerhead and gate flaring. As a result, transistors TrA through TrF can have substantially the same finished gate length.

Semiconductor device and method for fabricating the same

A circuit simulation apparatus has a means to acquire data regarding a transistor, a model parameter generation unit for generating a model parameter representing effects of stress upon the transistor active region caused by the isolation region, and a simulation execution unit for evaluating characteristics of the transistor using a simulation program associated with the model parameter. The model parameter includes a term regarding width of the transistor active region, a term regarding width of the peripheral active region, and a term regarding width between the transistor active region and the peripheral active region.

Circuit simulation method

A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.

Semiconductor device

In a cell comprising an N well and a P well, a distance SPfrom a center line of a contact N-type region to an N well end of the N well is set to be a distance which causes a transistor not to be affected by resist. A distance from a well boundary to the center line of the contact N-type region is equal to SP. A design on the P well is similar to that on the N well. Thereby, modeling of the transistor in the cell can be performed, taking into consideration an influence from resist in one direction. Also, by fabricating a cell array which satisfies the above-described conditions, design accuracy can be improved.

Mask layout design improvement in gate width direction

An integrated circuit includes: a first well of a first conductivity type; a second well of a second conductivity type coming into contact with the first well at a well boundary extending in a gate length direction; a first transistor having a first active region of the second conductivity type provided in the first well; and a second transistor which has a second active region of the second conductivity type provided in the first well and differing from the first active region in length in a gate width direction. The center location of the first active region in the gate width direction is aligned with the center location of the second active region in the gate width direction with reference to the well boundary.

Semiconductor integrated circuit

A CBCM circuit is capable of separately measuring each component of a measuring target capacitance. A node (N) is electrically connected to a terminal (P) between the drains of PMOS and NMOS transistors (MP, MN). As a target capacitance forming part, a coupling capacitance (C) is formed between the node (N) and a node (N). The node (N) is connected to a pad () through the terminal (P) and an NMOS transistor (MN), and a node (N) is connected to a terminal (P) between the drains of PMOS and NMOS transistors (MP, MN). A reference capacitance (C) is formed at the node (N) as a dummy capacitance. Currents (I, I) supplied from a power source to the nodes (N, N) are measured with current meters (), respectively and a current (I) induced from the node (N) and flowing to a ground level is measured with a current meter ().

Capacitance measurement circuit

A system for operation verification of a semiconductor integrated circuit has a central processing unit, a design layout memory unit storing design layout information including the design layout configuration of the semiconductor integrated circuit, and a predicted final layout memory storing a predicted final layout configuration predicted by the central processing unit by adding an optical proximity effect to the design layout configuration. The system further has a netlister which describes a procedure for causing the central processing unit to produce a plurality of net lists in which different physical values are registered for a common element in the predicted final layout configuration, a netlist memory unit the plurality of net lists, and a circuit simulator which describes a procedure for causing the central processing unit to perform operation verification of the semiconductor integrated circuit by using an arbitrary one of the plurality of net lists.

System and method for operation verification of semiconductor integrated circuit

An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.

Semiconductor device and method of manufacturing the same

PMISFETs and NMISFETs are placed in a capacitance measuring circuit. Each of interconnects is connected via the corresponding PMISFET through a charging voltage supply part to a power supply pad and via the corresponding NMISFET through a current sampling part to a current-monitoring pad. A current I can be measured by bringing a probe of an ammeter into contact with the current-monitoring pad.

A CBCM measurement device includes a PMIS transistor, an NMIS transistor, a first reference conductor section connected to a first node, a second reference conductor section, with a dummy capacitor being formed between the first and second reference conductor sections, a first test conductor section connected to a second node, and a second test conductor section, with a test capacitor being formed between the first and second test conductor sections. The transistors are turned ON/OFF by using control voltages Vand V, and the capacitance of a target capacitor in the test capacitor is measured based on currents flowing through the first and second nodes. The capacitance measurement precision is improved by, for example, increasing a dummy capacitance.

Semiconductor device and capacitance measurement method

It is an object to obtain a semiconductor device having a circuit for CBCM (Charge Based Capacitance Measurement) which can measure a capacitance value with high precision. An MOS transistor constituting a circuit for CBCM has the following structure. More specifically, source-drain regions () and (') are selectively formed in a surface of a body region (), and extension regions () and (&#x2032;) are extended from tip portions of the source-drain regions () and (&#x2032;) opposed to each other, respectively. A gate insulating filmis formed between the source-drain regions () and (&#x2032;) including the extension regions () and (&#x2032;) and a gate electrode () is formed on the gate insulating film (). A region corresponding to a pocket region(&#x2032;) in a conventional structure having a higher impurity concentration than that of a channel region is not formed in a tip portion of the extension region(&#x2032;) and a peripheral portion of the extension region ().

Semiconductor device and method of checking semiconductor storage device

In a production line for obtaining a final product by performing a plurality of process steps on each of a plurality of products, when one of the process steps is finished, measured data is obtained by measuring the characteristics of a product on which the process step has been performed. Based on the measured data obtained, the performance of a final product is expected. And based on the expected performance of the final product, the number of products estimatingly finished for each performance rank thereof is calculated.

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Kyoto, Japan

Kyoji Yamashita