Burr-brown Corporation

Kyoji Matsusako

Toshihiko Hamasaki

Toshio Murota

Yoshiaki Shinohara

Ei-ichi Arihara

A digital-to-analog converter is provided which compensates for relative errors among weighting elements used for D/A conversion. The converter includes a decoder, a rotator, and a weighting section. The rotator receives decoded signals from a decoder to produce rotated output signals for activating or deactivating a plurality of weighting elements, respectively, included in the weighting section. The rotated output signals assure that the same number of weighting elements are activated in each of a plurality of sub-periods of time constituting a main period of time of the D/A conversion and that each of the plurality of weighting elements is activated the same number of times during the whole main period.

Rotation system for correction of weighting element errors in

An interpolation DAC includes first and second registers connected to receive the X least significant and Y most significant bits of a digital input word, and are clocked to latch the X least significant bits and Y most significant bits at a first clock rate. An adder has a first group of X inputs, a second group of X inputs, X outputs, and a carry output. A third register has X inputs, and X outputs coupled to the second group of X inputs of the adder. The third register is clocked to latch the outputs of the adder at a second clock rate which is the oversampling ratio times faster than the first clock rate. A Y bit plus 1 bit DAC in which the 1 bit is a duplicate of the least significant of the Y bit section has its most significant Y bits coupled to receive the outputs of the second register. The duplicate LSB is connected to receive the carry output from the adder. A low pass filter responsive to the Y bit plus 1 bit DAC produces an analog output representative of a value of the digital input word. The digital-to-analog conversion rate of the Y bit section of the Y bit plus 1 bit DAC can be performed at the slow first clock rate.

Interpolation DAC and method

A digital-to-analog converter converts a digital word of M+N bits to an analog signal with reduced bit switching error, by providing a first group of M input conductors conducting the M most significant bits of the digital word, a second group of N input conductors conducting the N least significant bits of the digital word, and an M bit plus 1 adder having M inputs connected to a corresponding conductor of the first group. A signal representative of the most significant bit of the digital input word is coupled to an input of the adder. The adder has M output conductors. Signals on the N input conductors of the second group together with signals on the M output conductors from an intermediate digital word of M+N bits differ in value from the first digital word. An M+N bit DAC receives the intermediate digital word and produces an analog current corresponding to the value of the intermediate digital word. A switched current source responsive to the most significant bit of the digital input word produces an offset current and algebraically sums it with the analog current to produce an analog output current. The offset current has a value equal in magnitude and opposite in polarity to the shift in the analog current produced by the coupling of the most significant bit of the digital input word to the input of the adder such that the analog output current corresponds to the value of the first digital word.

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Kanagawa, Japan

Kyoji Matsusako