Hitachi, Ltd.

Other

Renesas Technology Corp.

Hitachi Engineering Co., Ltd.

Kyoichiro Asayama

Hiroyuki Miyazawa

Hiroyuki Uchiyama

Yutaka Kobayashi

Yoshiyuki Kaneko

Kozo Watanabe

Masaki Nagao

Atushi Ogishima

Naokatsu Suwanai

Hiroki Soeda

Kazuya Endo

Takashi Yoneoka

Shuji Ikeda

Naotaka Hashimoto

Seigou Yukutake

Koichiro Ishibashi

Toshiaki Yamanaka

Satoshi Meguro

Masayuki Kojima

Atsuyoshi Koike

Jun Murata

Akihiro Tamba

Sadayuki Morita

Kazuyuki Suko

Fumiyuki Kanai

Tomoyuki Someya

Yasuo Kiguchi

Toshiro Aoto

Hideyuki Miyazawa

Eri Fujita

Kazumasa Yanagisawa

Ryoichi Hori

Goro Kitsukawa

Yutaka Hoshino

Yasuhiro Mitsui

Yasuko Yoshida

Keiichi Yoshizumi

Yuzuru Ohji

Shiro Kamohara

Kazushi Fukuda

Seigoh Yukutake

Satoru Haga

Eri Okamoto

Akihiro Tanba

Yuuki Koide

Fumiko Arakawa

Disclosed is a technique capable of improving a yield of a semiconductor device by measuring a plurality of TEGs arranged in a scribe region. A first electrode pad connected to each terminal of a TEG is formed as a rectangular, minute, isolated pattern having a side length of about 0.5 &#x3bc;m or shorter and constituted of an uppermost layer wiring on a semiconductor substrate, and therefore, a great number of TEGs can be laid in a first scribe region. The characteristic evaluation or the failure analysis is performed by contacting a nanoprobe having a tip radius of curvature of 0.05 &#x3bc;m to 0.8 &#x3bc;m to the first electrode pad.

Method of manufacturing a semiconductor device to provide a plurality of test element groups (TEGs) in a scribe region

A static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit made of driver MISFETs and load MISFETs. The top of the load MISFETs is covered with supply voltage lines so that capacitor elements of a stacked structure are formed between the gate electrodes of the load MISFETs and the supply voltage lines.

Semiconductor integrated circuit device

Semiconductor memory device having driver and load MISFETs and capacitor elements

In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region as a memory cell array region a first MISFET having a gate electrode and source and drain regions; first and second capacity electrodes and a dielectric film extending onto a first insulating film on the gate electrode; a second insulating film positioned on the second capacity electrode; and a first wiring positioned on the second insulating film, while in a second region as a peripheral circuit region there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a third insulating film on the first insulating film; a second insulating film on the third insulating film; and a second wiring on the second insulating film.

Semiconductor memory circuit device and method for fabricating a

When the source and drain regions (an n.sup.- type semiconductor region and an n.sup.+ type semiconductor region) of a complementary MISFET and a p-type semiconductor region for use as a punch-through stopper are formed in a p-type well in a substrate having a p- and an n-type well, p-type impurities for the punch-through stopper are suppressed from being supplied to the feeding portion (an n.sup.+ type semiconductor region) of the n-type well.

Process for producing semiconductor integrated circuit

Method of making a semiconductor memory circuit device

A semiconductor integrated circuit device includes a dielectric breakdown prevention circuit coupled to an external terminal for protecting an input stage circuit. The prevention circuit has bipolar transistors and complementary MISFETs including a first MISFET of a first conductivity type and a second MISFET of a second conductivity type. A first semiconductor region of the first conductivity type is formed by the same layer as a well region in which the second MISFET is formed. A second semiconductor region of the second conductivity type is formed in said first semiconductor region by the same layer as source and drain regions of the second MISFET. These first and second semiconductor regions form a first PN junction diode. The external terminal is electrically coupled to one end portion of said second semiconductor region. A high impurity conductivity type buried third semiconductor region underlies the said second semiconductor region, and is formed by the same layer as a region isolating the bipolar transistors. This third region is disposed at the bottom surface of said first semiconductor region. A fourth semiconductor region of the second conductivity type is also formed in said first semiconductor region by the same layer used for collector contact regions of the bipolar transistors, and is connected with another end portion of said second semiconductor region, in contact with the third semiconductor region. The fourth semiconductor region is coupled to the input stage circuit, and the third and fourth semiconductor regions form a second PN junction diode.

Semiconductor integrated circuit device including a dielectric breakdown

In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region, which is a memory cell array region, a first MISFET having a gate electrode and source and drain regions; first and second capacitor electrodes and a dielectric film extended over a first insulating film and over the gate electrode; a second insulating film disposed on the second capacitor electrode; a third insulating film interposed between the first insulating film and first capacitor electrode; and a first wiring positioned on the second insulating film. In a second region of the device, which is a peripheral circuit region, there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a second insulating film on a third insulating film, the third insulating film being interposed between the first and second insulating films; and a second wiring on the second insulating film. The second wiring is formed by the same level conductor layer as that forming the first wiring. Similarly, the first through third insulating films of the first region are correspondingly associated with the first through third insulating films of the second region, respectively.

Semiconductor memory circuit device and method for fabricating same

A semiconductor integrated circuit device is equipped with a DRAM whose memory cell is formed as a series circuit of a memory cell selection MISFET and a data storage capacitance element of a stacked structure. A complementary data line extends on an upper electrode layer of the data storage capacitance element of the stacked structure through an inter-level insulation film which is connected to a semiconductor region of the memory cell selection MISFET. To reduce parasitic capacitance the wiring width of the complementary data line is formed to be smaller than the film thickness of the inter-level insulation film between the complementary data line and the upper electrode layer of said data storage capacitance element of the stacked structure.

A small and reliable semiconductor device is provided in a substrate which has an isolation trench and a capacitor trench. The isolation trench isolates a bipolar transistor from other semiconductor devices, and the capacitor trench provides capacitance to a memory cell which is formed in the substrate. The interior of the device isolation trench is kept in a floating state with respect to the surrounding semiconductor regions by forming an insulating film over the inner surface of the trench. In the capacitor trench, insulating layers and resilient conductive layers are formed alternately to form capacitance between the opposing conductive layers.

Semiconductor device including an improved trench arrangement

A method for producing a memory LSI having in its peripheral circuitry an MISFET of LDD structure and a vertical type bipolar transistor is disclosed. More particularly, an impurity for forming a low impurity concentration region of the said MISFET of LDD structure is introduced sideways of an emitter-base junction of the bipolar transistor. By the introduction of the said impurity, an effective impurity concentration near the base surface is reduced and the cut-off frequency of the bipolar transistor is improved.

Method for producing semiconductor integrated circuit device

Growing community of inventors

Tachikawa, Japan

Kyoichiro Asayama