Advanced Micro Devices Corporation

Kyle Viau

James Vinh

Srikanth Arekapudi

Ganesh Venkataramanan

Visvesh S Sathe

Charles Ouyang

A resonant clock network includes an inductor coupled to the clock network through a plurality of switches. When the clock network enters resonant mode, the turn-on of the switches to couple the inductor to the clock network is staggered. The clock network may be formed of multiple regions, each with its own inductor and switches. The turn-on of switches of each region may be staggered with respect to the turn-on off the switches of the other regions as well as to the turn-on of switches within a region. In addition to staggering the turn-on of the switches when entering the resonant mode, the switches may be turned off in a staggered manner when exiting the resonant mode of operation.

Transitioning between resonant clocking mode and conventional clocking mode

Content-Addressable Memory (CAM) arrays and related circuitry for integrated circuits and CAM array comparison methods are provided such that relatively low power is used in the operation of the CAM circuitry. A binary value pair is stored in a pair of CAM memory elements. A comparison signal is provided to comparator circuitry that uniquely represents the stored binary values. A match signal is input to the comparator circuitry that uniquely represents a binary value pair to be compared with the stored binary value pair. In one example, a transistor is operated to output a positive match result signal only on a condition that the comparison signal provided to the comparator circuitry and match signal input to the comparator circuitry represent the same binary value pair. In that example, no transistor of the comparator circuitry is operated when the comparison signal provided to the comparator circuitry and match signal input to the comparator circuitry represent different binary value pairs.

Low power content-addressable memory and method

A complementary metal oxide semiconductor (CMOS) circuit is described. The CMOS circuit includes a plurality of CMOS gates, a plurality of logic inputs and a logic output. Each CMOS gate is connected to a negative power supply terminal (Vss) and a positive power supply terminal (Vdd). The CMOS circuit further includes parasitic nets connected to the CMOS gates, and net pulldown circuits for eliminating a charge accumulation on the parasitic nets while avoiding potential short circuit conditions. The CMOS gates may be OR-AND-INVERT (OAI) gates or AND-OR-INVERT (AOI) gates.

Growing community of inventors

Fremont, CA, United States of America

Kyle Viau