Vishay-siliconix

Siliconix Incorporated

Siliconix Technology C. V.

Vishay-silconix

Kyle Terrill

Kuo-In Chen

Deva N Pattanayak

Qufei Chen

Sharon Shi

Robert Xu

Kam Hong Lui

Mohamed N Darwish

Ayman Shibib

Yuming Bai

Chanho Park

Frederick Perry Giles

Christiana Yue

The-Tu Chau

M Ayman Shibib

Ronald Wong

Yang Gao

Misbah Ul Azam

Jainhai Qi

Madhur Bobde

Frank Kuo

Sen Mao

Wenjie Zhang

Lingpeng Guan

King Owyang

Jun Hu

Reuven Katraro

Mohammed Kasem

Hamilton Lu

Zhiyun Luo

Trang Vu

Martin Hernandez

Karl Lichtenberger

Misha Lee

Jason Qi

Seokjin Jo

Yongping Ding

Jinman Yang

Calvin Choi

Hamza Yilmaz

Min Luo

John Huang

Peter Dang

Min-Yih Luo

Chrisoph Werres

Christoph Werren

David Chang

Ben Chan

Wharton McDaniel

Gao Yang

Christina Yue

Robert Q Xu

A vertical trench shield device can include a plurality of gate structures and a termination structure surrounding the plurality of gate structures. The plurality of gate structures can include a plurality of gate regions and a corresponding plurality of gate shield regions. The plurality of gate structures can be disposed between the plurality of source regions, and extending through the plurality of body regions to the drift region. The plurality of gate structures can be separated from each other by a first predetermined spacing in a core area. A first set of the plurality of gate structures can extend fully to the termination structure. The ends of a second set of the plurality of gate structures can be separated from the termination structure by a second predetermined spacing. The first and second spacings can be configured to balance charge in the core area and the termination area in a reverse bias condition.

Methods of manufacture of termination for vertical trench shielded devices

A method of fabricating semiconductor devices including epitaxially depositing a heavily doped substrate layer that is substantially free of crystalline defects on a lightly doped virtual substrate. The device regions of the semiconductor devices can be fabricated about the heavily doped substrate layer before the lightly doped virtual substrate is removed.

Virtual wafer techniques for fabricating semiconductor devices

A transistor and method of manufacturing an electrically active chip seal ring surrounding the gate, gate insulator and source structure of the active core area of the transistor. The chip seal ring can be electrically coupled to the gate to seal the active core area from intrusions of contaminants, impurities, defects and or the like.

Transistors with electrically active chip seal ring and methods of manufacture

Split gate semiconductor with non-uniform trench oxide. A metal oxide semiconductor field effect transistor (MOSFET) comprises a plurality of parallel trenches. Each such trench comprises a first electrode coupled to a gate terminal of the MOSFET and a second electrode, physically and electrically isolated from the first electrode. The second electrode is beneath the first electrode in the trench. The second electrode includes at least two different widths at different depths below a primary surface of the MOSFET. The trenches may be formed in an epitaxial layer. The epitaxial layer may have a non-uniform doping profile with respect to depth below a primary surface of the MOSFET. The second electrode may be electrically coupled to a source terminal of the MOSFET.

Split gate semiconductor with non-uniform trench oxide

A semiconductor device includes a first group of trench-like structures and a second group of trench-like structures. Each trench-like structure in the first group includes a gate electrode contacted to gate metal and a source electrode contacted to source metal. Each of the trench-like structures in the second group is disabled. The second group of disabled trench-like structures is interleaved with the first group of trench-like structures.

Semiconductor device having reduced gate charges and superior figure of merit

Disclosed are semiconductor devices that include additional gate pads, and methods of fabricating and testing such devices. A device may include a first gate pad, a second gate pad, and a third gate pad. The first gate pad is connected to a gate including a gate oxide layer. The second and third gate pads are part of an electro-static discharge (ESD) protection network for the device. The ESD protection network is initially isolated from the first gate pad and hence from the gate and gate oxide layer. Accordingly, gate oxide integrity (GOI) testing can be effectively performed and the reliability and quality of the gate oxide layer can be checked. The second gate pad can be subsequently connected to the first gate pad to enable the ESD protection network, and the third gate pad can be subsequently connected to an external terminal when the device is packaged.

Semiconductor device having multiple gate pads

Termination for vertical trench shielded devices

Trench MOSFET with self-aligned body contact with spacer. In accordance with an embodiment of the present invention, a plurality of gate trenches are formed into a semiconductor substrate. A body contact trench is formed into the semiconductor substrate in a mesa between the gate trenches. Spacers are deposited on sidewalls of the body contact trench. An ohmic body contact is implanted into the semiconductor substrate through the body contact trench utilizing the spacers to self-align the implant. A body contact trench extension may be etched into the semiconductor substrate through the body contact trench utilizing the spacers to self-align the etch, prior to the implant.

Trench MOSFET with self-aligned body contact with spacer

Trench MOSFET with self-aligned body contact with spacer. In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor substrate, and at least two gate trenches formed in the semiconductor substrate. Each of the trenches comprises a gate electrode. The semiconductor device also includes a body contact trench formed in the semiconductor substrate between the gate trenches. The body contact trench has a lower width at the bottom of the body contact trench and an ohmic body contact implant beneath the body contact trench. The horizontal extent of the ohmic body contact implant is not greater than the lower width of the body contact trench.

A high-electron-mobility transistor (HEMT) includes a substrate layer of silicon, a first contact disposed on a first surface of the substrate layer, and a number of layers disposed on a second surface of the substrate layer opposite the first surface. A second contact and a gate contact are disposed on those layers. A trench containing conducting material extends completely through the layers and into the substrate layer. In an embodiment of the HEMT, the first contact is a drain contact and the second contact is a source contact. In another embodiment of the HEMT, the first contact is a source contact and the second contact is a drain contact.

High-electron-mobility transistor with buried interconnect

A device includes a first high electronic mobility transistor (HEMT) and a second HEMT. The first HEMT includes a first gate, a source coupled to the first gate, and a drain coupled to the first gate. The second HEMT includes a second gate coupled to the source and to the drain. The second HEMT has a lower threshold voltage than the first HEMT.

High-electron-mobility transistor devices

Presented systems and methods can facilitate efficient switching and protection in electronic systems. A system can comprise: an input operable to receive a signal; an adjustable component configurable to operate in a first mode which includes a low resistance and the component configurable to operate in a second mode which includes a current limiting operation in which the second mode enables continued operation in conditions that are unsafe for operation in the first mode; and an output operable to forward a signal. The adjustable component can be configurable to turn off if unsafe to operate in either the first mode or second mode. The first mode can include a relatively large component configuration with a relatively low drain to source on resistance. Utilizing a small component configuration in the second mode can include a relatively increased gate to source voltage compared to a large component configuration in the second mode.

Current limiting systems and methods

In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and the source that are located on a first surface of the second die and a drain that is located on a second surface of the second die that is opposite the first surface.

Method for fabricating stack die package

Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.

System and method for substrate wafer back side and edge cross section seals

First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.

Structures and methods of fabricating dual gate devices

Growing community of inventors

Santa Clara, CA, United States of America

Kyle Terrill