International Business Machines Corporation

Kyle Phillips

Daniel Gatlin Saconn

Edward C McCain

Lahiruka Winter

Dominic Schroeder

Craig M Slegel

Adeoye O Owolabi

Connor Nace

Cara Hanson

Zachary Neumann

Ronald Asomah Dartey

A system for testing a design of a computing component includes an input device configured to receive a request to perform a test of a component, and a testing unit including a simulation of the component. The simulation is configured to output a result indicative of a response to a set of instruction addresses, the set of instruction addresses is acquired from a plurality of addresses, and the plurality of addresses including a plurality of address groups, where each address group is associated with a respective group identifier. The system also includes a plurality of requestors configured to apply the set of instruction addresses to the simulation, where a requestor of the plurality of requestors is configured to select an address for application to the simulation based on a received group identifier and a variably configurable weight value assigned to the received group identifier and the requestor.

Configuration of weighted address pools for component design verification

Aspects of the invention include a method for providing a master computing environment containing a master repository. The method periodically conducts a search of proprietary data repositories and causes the master computing environment to create a merged collection in the master repository after the periodical conducted search of the proprietary data repositories. The method correlates metadata with the proprietary data repositories and puts the correlated metadata into the master repository. The method sets up a question feeder server to receive queries and to pass the queries to the master computing environment. The method causes the master computing environment to provide results in response to a query, where the master computing environment acts as an autonomous information provider that finds and sorts subject matter on a proprietary development project.

Advanced search and document retrieval for development and verification system prototypes

Systems and methods to implement performance monitoring of a device under test involve defining one or more sequences. Each of the one or more sequences includes two or more events, each of the two or more events being defined by one or more hardware signals that include a hardware register value, transmission of a message or signal, or a wire voltage change. A method includes initiating a simulation of the device under test by inputting one or more signals at one or more inputs of the device under test for propagation across the device under test, and monitoring completion of the two or more events defining each of the one or more sequences. Performance of the device under test is reported. Reporting includes providing latency of each of the one or more sequences. A final design of the device under test is provided for fabrication based on the performance monitoring.

Modular event-based performance monitoring in integrated circuit development

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Poughkeepsie, NY, United States of America

Kyle Phillips