Intel Corporation

Kyle Markley

David W Grawrock

Bruce Querbach

Tieyu Zheng

Keshavan K Tiruvallur

Mark B Trobough

Chinna B Prudvi

Vui Yong Liew

Hermann Gartler

Ashok N Kabadi

Samie B Samaan

Keith A Drescher

Mukesh Kataria

Jay Joseph Nejedlo

Lyle E Cool

Russell J Wunderlich

James J Grealish

Brian Meyer

Abhijit Davare

Priyadarsan Patra

William Penner

Ridvan A Sahan

Rahima K Mohammed

Arun R Ramadorai

Wee Hoo Cheah

Kapila B Udawatta

Yuen Tat Lee

John L Baudrexl

Loren James McConnell

Kip C Killpack

Christian E Iovin

Sanjay S Salem

Travis K Goff

David C Florey

Evan J Halprin

Jiun Long Foo

Selvakumar Raja Gopal

Neil Dobler

Nagib Z Hakim

Timothy S Storey

Yi Amy Xia

Edwin E Parks

Padmakumar Gopal

An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

Test, validation, and debug architecture

A mechanism to obtain a quiescence state for a component coupled to a bidirectional communications interface is obtained. A transition to quiescence may be may by activating a first defeature in the component to cause messages received over a communication bus coupled between the component and another component to be ignored, and activating a second defeature in the component to prevent messages from being sent over the communication bus by the component. Operations may then be performed on the component while the defeatures are activated.

Quiescence for retry messages on bidirectional communications interface

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Hillsboro, OR, United States of America

Kyle Markley