At&t Laboratories, Limited

Kyle L Burson

Apparajan Ganesan

Scott H Early

Two input stages (10,12) are interconnected so that their input common mode voltage ranges to one side of signal ground are combined to provide a common mode voltage range substantially equal to the supply voltage. One stage has N-channel differential input transistors (N1,N2), while the other stage has P-channel differential input transistors (P3,P4). The input current branches of the stages are interconnected by current mirror transistors (N6,N7) so that signal current is shared. The output (22) is taken from one branch of the N-type stage (10) and coupled to an output stage (24) with frequency compensation (C,R).

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Indianapolis, IN, United States of America

Kyle L Burson