Drexel University

Tufts College

Kyle Juretus

Ioannis Savidis

Kapil R Dandekar

Cem Sahin

Nagarajan Kandasamy

James J Chacko

Marko Jacovic

Vaibhav Venugopal Rao

Ioannis Savadis

Eric Miller

David Werner

Mark Hempstead

A state machine system on a chip presents hidden state transitions to create IC knowledge not available in a logical netlist and temporal key dependencies to increase the difficulty of executing the SAT attack. The change in the state space of a circuit over time may be used to increase circuit security. Hidden transitions that are frequency dependent, state dependent keys, and temporally dependent transition keys may be used as ways to increase security against SAT based attacks.

Enhanced circuity security through hidden state transitions

A proposed technique allows for the security of the logic cone through logic locking and secures the outputs of the circuit from the scan chain without modifications to the structure of the scan chain. Since the oracle responses in test mode do not correspond to the functional key, satisfiability (SAT) attacks are not able to leverage the responses from the scan chain. In addition, a charge accumulation circuit is developed to prevent and detect any attempt to enter the partitioned test mode while the correct circuit responses are still stored within the registers.

Reducing logic locking key leakage through the scan chain

In some embodiments, the present disclosure provides systems and methods for detecting malware, including receiving thermal images of an integrated circuit, and generating a power density profile using at least one of the thermal images. The present disclosure further includes comparing the power density profile to an expected power density profile of the integrated circuit, and determining, based on the comparison, if the integrated circuit is in an abnormal operating state.

Systems and methods for thermal side-channel analysis and malware detection

A key-based interleaver for enhancement the security of wireless communication includes a physical layer communication channel key to provide security even when the software encryption key is compromised. A method of creating a secure communication link using a physical layer interleaving system includes implementing a key policy implementation that utilizes temporal dependency and interleaving bits using a flexible inter and intra-block data interleaver.

Physical layer key based interleaving for secure wireless communication

There are several approaches to encrypting circuits: combination logic encryption, encrypted gate topologies, transmission gate topologies, and key expansion of gate topologies. One of the approaches provides a circuit having a gate topology comprising a logic gate with integrated key transistors, where the key transistors comprise at least a PMOS stack and an NMOS stack. The PMOS stack comprises a first PMOS switch and a second PMOS switch, where the first and the second PMOS switches have sources to a voltage source and drains that serve as a source to a third PMOS switch. The NMOS stack comprises a first NMOS switch and a second NMOS switch, where the first and the second NMOS switches have sources to ground and drains that serve as a source to a third NMOS switch. Each of the above approaches may encrypt a circuit with certain advantages in delay and power consumption.

Reduced overhead gate level logic encryption

The transition to a horizontal integrated circuit (IC) design flow has raised concerns regarding the security and protection of IC intellectual property (IP). Obfuscation of an IC has been explored as a potential methodology to protect IP in both the digital and analog domains in isolation. However, novel methods are required for analog mixed-signal circuits that both enhance the current disjoint implementations of analog and digital security measures and prevent an independent adversarial attack of each domain. A methodology generates functional and behavioral dependencies between the analog and digital domains that results in an increase in the adversarial key search space. The dependencies between the analog and digital keys result in a 3&#xd7; increase in the number of iterations required to complete the SAT attack.

Securing analog mixed-signal integrated circuits through shared dependencies

A physical layer based technique secures wireless communication between a transmitter and receiver. The technique involves obfuscating the preamble data of the baseband signal through unique keys that are generated at the transmitter and the receiver based on channel characteristics known only to them.

Physical gate based preamble obfuscation for securing wireless communication

A key based technique that targets obfuscation of critical circuit parameters of an analog circuit block by masking physical characteristics of a transistor (width and length) and the circuit parameters reliant upon these physical characteristics (i.e. circuit biasing conditions, phase noise profile, bandwidth, gain, noise figure, operating frequency, etc.). The proposed key based obfuscation technique targets the physical dimensions of the transistors used to set the optimal biasing conditions. The widths and/or lengths of a transistor are obfuscated and, based on an applied key sequence, provides a range of potential biasing points. Only when the correct key sequence is applied and certain transistor(s) are active, are the correct biasing conditions at the target node set.

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Quakertown, PA, United States of America

Kyle Juretus