Texas Instruments Corporation

Kyle Clifton Schulmeyer

Roger A Cline

Md Abidur Rahman

Charvaka Duvvury

Sualp Aras

Vikrant Dhamdhere

Ponnarith Pok

Abidur Rahman

Eung Jung Kim

Xiaochun Zhao

Cynthia Ann Torres

A system includes a clamp network coupled between an input and an output and configured to clamp a voltage between the input and the output to a first clamp voltage based on the presence of a trigger signal and to a second clamp voltage based on the absence of the trigger signal. The second clamp voltage is greater than the first clamp voltage and the first clamp voltage is less than a breakdown voltage of the power transistor device. A detector circuit is coupled to the input and the output. A power transistor device may also be coupled between the input and the output. The detector circuit is configured to detect a pulse signal at the input or the output while the power transistor device is off and to generate the trigger signal for a time interval based on detecting the pulse signal.

Clamp for power transistor device

An output discharge circuit for a load switch may include a capacitor coupled between a power rail of the output discharge circuit and a ground lead, and a diode coupled between a power input of the output discharge circuit and the power rail. The output discharge circuit may charge the capacitor via a current path formed by the diode while power is being supplied to the load switch. When the power supply to the output discharge circuit is turned off, the diode may prevent the capacitor from discharging through the current path, and the stored charge on the capacitor may be used to power the output discharge switch for a period of time after the power supply has been turned off. In this way, the output discharge circuit may continue to discharge the output of the load switch even when power is no longer being supplied to the load switch.

Output discharge techniques for load switches

A circuit for protecting against electrostatic discharge events has a semiconductor substrate () of first conductivity embedding a first diode in a well () of opposite second conductivity, the diode's anode () tied to an I/O pin-to-be-protected () at a first voltage, and the first diode's cathode () connected to the first drain () of a first MOS transistor in the substrate. The first MOS transistor's first gate () is biased to a second voltage smaller than the first voltage, thereby reducing the first voltage by the amount of the second voltage. In series with the first MOS transistor is a second MOS transistor with its second drain () merged with the first source of the first MOS transistor, and its second source (), together with its second gate (), tied to ground potential ().

Electrostatic discharge protection device for high voltage

An apparatus includes a FET device having a drain terminal, source terminal and a gate terminal; a first supply voltage coupled to the drain terminal of the FET; an output terminal coupled to the source terminal of the FET; a bias current supply coupled to the gate terminal of the FET; a second supply voltage coupled to the gate terminal of the FET; a current sensing circuit coupled to output a sense current proportional to the current flowing through the FET; a current limit comparator coupled to the sense current and comparing the sense current to a predetermined limit current; a pull down current circuit coupled to remove current from the gate terminal of the FET; a current time derivative circuit coupled to the sense current and outputting a sense rate current; and a circuit coupled to receive the sense rate current and coupled to the bias current supply.

Methods and apparatus for continuous current limiting for FETS in high inductive load systems

An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device.

ESD protection using diode-isolated gate-grounded nMOS with diode string

ESD protection apparatus disclosed herein include an ESD trigger circuit to sense the occurrence of an ESD event and an ESD discharge device to provide a low impedance path to ground through which to discharge energy associated with the ESD pulse. Some embodiments also include a VDD turn-on clamp to prevent the ESD discharge device from switching to a conductive state during a VDD power-on event. Some embodiments further include a VDD glitch clamp to prevent a switching pulse triggered by a transient disruption in the VDD supply from propagating to the ESD discharge device and causing the ESD discharge device to conduct in the absence of an ESD event.

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Dallas, TX, United States of America

Kyle Clifton Schulmeyer