Altera Corporation

Kyle Bowers

Cheng-Hsiung Huang

Naresh U Mehta

Parmeshwar Reddy Bayappu

Integrated circuits with electrostatic discharge (ESD) protection circuitry are provided. Integrated circuits may include input-output pins that are coupled to the ESD protection circuitry. The ESD protection circuitry may include diode circuits, a control circuit, and a power clamp circuit. Each diode circuit may have a first terminal that is coupled to a respective input-output pin and a second terminal that is coupled to a shared ESD control line. The control circuit may supply a boosted voltage onto the control line to reverse bias the diode circuits during normal operation while the power clamp is turned off. During an ESD event, the power clamp may be turned on to sink current from the diode circuits. The power clamp may include a transistor having a substrate that is forward biased to improve transistor drive strength during the ESD event and that is reverse biased to reduce leakage during normal operation.

Electrostatic discharge protection circuitry with reduced capacitance

An electrostatic discharge (ESD) protection circuit includes an electrostatic discharge bus, first and second resistors coupled in series, first and second capacitors coupled in series, and first and second transistors. The first resistor is coupled to the electrostatic discharge bus. The first capacitor is coupled to the second resistor. The first transistor has a control input that is coupled between the first and the second resistors. The second transistor has a control input that is coupled between the first and the second capacitors.

Electrostatic discharge protection circuits and methods

A method for managing testing of test material is disclosed. An electronic traveler associated with the test material is identified. The test materials are tested as specified by the electronic traveler. Test results from the tests are recorded onto the electronic traveler.

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Morgan Hill, CA, United States of America

Kyle Bowers