International Rectifier Corporation

Kyle A Spring

Jianjun Cao

Daniel Marvin Kinzer

Perry L Merrill

Ling Ma

Timothy Donald Henson

Thomas Herman

Naresh Thapar

Robert J Montgomery

Adam I Amali

Ashita Mirchandani

Donald He

Ritu Sodhi

Siddharth Kiyawat

Paul Harvey

David Paul Jones

Hugo R Burke

Harold E Davis

David Kent

Ying Xiao

Dave Kent

Cao Jianjun

Devana Cohen

A short channel trench MOSFET which has a lower peak concentration of dopants and a substantially uniform concentration of dopants compared to a conventional short channel device.

Short channel trench power MOSFET with low threshold voltage

The active area of a current sense die is surrounded by a transition region which extends to the terminating periphery of the die. Spaced parallel MOSgated trenches extend through and define an active area. The trench positions in the transition region are eliminated or are deactivated, as by shorting to the MOSFET source of the trench, or by removing the source regions in areas of the transition region. By inactivating MOSgate action in the transition region surrounding the source, the device is made less sensitive to current ratio variation due to varying manufacturing tolerances. The gate to source capacitance is increased by surrounding the active area with an enlarged Pfield region which is at least five times the area of the active region, thereby to make the device less sensitive to ESD failure.

Current sense trench type MOSFET with improved accuracy and ESD withstand capability

A trench power semiconductor device including a recessed termination structure.

Trench MOSFET technology for DC-DC converter applications

One or more enhancement mode GaN devices has a stress-reduced gate region which interrupts the normally conductive 2Deg layer. A piezoelectric film is disposed over the stress-reduced gate region and can be excited to deflect and apply a stress to the stress reduced gate region to reintroduce the conductive 2Deg layer in that region and to turn on the device. A depletion mode segment may also be provided.

Enhancement mode GaN FET with piezoelectric gate

A trench type power semiconductor device includes proud gate electrodes that extend out of the trenches and above the surface of the semiconductor body. These proud gate electrodes allow for making ultra-shallow source regions within the semiconductor body using, for example, a low temperature source drive. In addition, a method for manufacturing the trench type power semiconductor device includes a low temperature process flow once the gate electrodes are formed.

Low temperature process and structures for polycide power MOSFET with ultra-shallow source

A trench type top drain MOSgated device has a drain electrode on the die top and a source electrode on the die bottom surface. The device is turned on by a control voltage connected between a drain and a gate region. The device cell has a body short trench and a gate trench. Gate poly is disposed in the bottom of the gate trench and is disposed adjacent a thin gate oxide lining a channel region with minimum overlap of the drain drift region. The bottom of the body short trench contains a contact which shorts the body region to the channel region. The body short, top drain region and gate polysilicon are simultaneously silicided. The gate trench is widened at its top to improve Qcharacteristics. Both the body short trench and gate trench are simultaneously filled with gap fill material.

Top drain MOSgated device and process of manufacture therefor

A fabrication process for a trench type power semiconductor device includes forming inside spacers over a semiconductor surface. Using the spacers as masks, trenches with gates are formed in the semiconductor body. After removing the spacers, source implants are formed in the semiconductor body along the trench edges and are then driven. Insulation caps are then formed over the trenches. Outside spacers are next formed along the sides of the caps. Using these spacers as masks, the semiconductor surface is etched and high conductivity contact regions formed. The outside spacers are then removed and source and drain contacts formed. Alternatively, the source implants are not driven. Rather, prior to outside spacer formation a second source implant is performed. The outside spacers are then formed, portions of the second source implant etched, any remaining source implant driven, and the contact regions formed. The gate electrodes are either recessed below or extend above the semiconductor surface.

Trench power MOSFET fabrication using inside/outside spacers

A method for manufacturing a trench type power semiconductor device which includes process steps for forming proud gate electrodes in order to decrease the resistivity thereof.

Trench power MOSFET with reduced gate resistance

A trench MOS-gated semiconductor device that includes field relief regions formed below its base region to improve its breakdown voltage, and method for its manufacturing.

Trench mosfet with field relief feature

A vertical MOSFET has a substrate of a first conductivity type. A channel region of a second conductivity type is diffused into the substrate. A gate is disposed at least partially over the channel region. A source region of a second conductivity type is disposed proximate to the gate and adjacent to the channel region. The channel region includes a depletion implant area proximate to the gate. The depletion implant species is of the second conductivity type to reduce the concentration of the first conductivity type in the channel region without increasing the conductivity in the drain/drift region.

Depletion implant for power MOSFET

A process for forming a superjunction device that includes a series of implants to form closely spaced implant regions which are linked together by a short thermal step, whereby deep and narrow regions can be formed within a semiconductor body.

Superjunction device and method of manufacture therefor

A process for manufacturing a semiconductor device of the trench variety with reduced feature sizes and improved characteristics which process includes forming a termination structure having a field oxide disposed in a recess below the surface of the semiconductor die in which the active elements of the device are formed, and forming source regions after the major thermal steps have been performed.

Method for manufacturing a semiconductor device with a trench termination

A process for forming a power MOSFET enables the connection a metal gate electrode to the conductive polysilicon gates in the active area without an additional mask step. In the process, a groove is formed in the field oxide during the active area mask step. Conductive polysilicon is then formed over the active area and into the groove. At least one window is formed over the groove along with the mask window for forming the channel and source implant windows, and the polysilicon is etched to the silicon surface in the active area, but a strip is left in the groove. This strip is contacted by gate metal during metal deposition. Thus, gate metal is connected to the polysilicon without an added mask step.

Reduced mask count process for manufacture of mosgated device

A MOS-gated semiconductor device is shown and described which includes deep implanted junctions and thick oxide spacers disposed over a substantial portion of common conduction regions.

Growing community of inventors

Hawthorne, CA, United States of America

Kyle A Spring