Rebellions Inc.

Kyeongryeol Bong

Jinwook Oh

Jinseok Kim

Wongyu Shin

Chang-Hyo Yu

Yoonho Boo

Juyeong Yoon

Donghan Kim

A neural processing device is provided. The neural processing device comprises a plurality of neural processors, a shared memory shared by the plurality of neural processors, a plurality of semaphore memories, and global interconnection. The plurality of neural processors generates a plurality of L3 sync targets, respectively. Each semaphore memory is associated with a respective one of the plurality of neural processors, and the plurality of semaphore memories receive and store the plurality of L3 sync targets, respectively. Synchronization of the plurality of neural processors is performed according to the plurality of L3 sync targets. The global interconnection connects the plurality of neural processors with the shared memory, and comprises an L3 sync channel through which an L3 synchronization signal corresponding to at least one L3 sync target is transmitted.

Neural processing device and method for synchronization thereof

A neural core, a neural processing device including same and a method for lauding data of a neural processing device are provided. The neural core comprises a processing unit configured to perform operations, an L0 memory configured to store input data and an LSU configured to perform a load task and a store task of data between the processing unit and the L0 memory, wherein the LSU comprises a local memory load unit configured to transmit the input data in the L0 memory to the processing unit, and the local memory load unit comprises a target decision module configured to identify and retrieve the input data in the L0 memory, a transformation logic configured to transform the input data and thereby generate transformed data and an output FIFO configured to receive the transformed data and transmit the transformed data to the processing unit in the received order.

Neural core, neural processing device including same, and method for loading data of neural processing device

A neural processing device and transaction tracking method thereof are provided. The neural processing device comprises a first set of a plurality of neural cores, a shared memory shared by the first set of the plurality of neural cores, and a programmable hardware transactional memory (PHTM) configured to receive a memory access request directed to the shared memory from the first set of the plurality of neural cores and configured to commit or buffer the memory access request.

Neural processing device and transaction tracking method thereof

A Field Programmable Gate Array (FPGA) system includes a main FPGA and one or more sub-FPGAs connected to the main FPGA. The main FPGA is configured to detect a positive edge of a pulse included in a user clock using a sampling clock of the main FPGA, generate a flag using the detected positive edge, generate a clock packet indicating the generated flag, and provide the generated clock packet to any one of the one or more sub-FPGAs.

Field Programmable Gate Array system

A neural processing device is provided. The neural processing device comprises: a processing unit configured to receive an input activation and a weight and perform a two-dimensional matrix calculation with the input activation and the weight to generate an output activation, a first memory, and a load-store unit (LSU) configured to perform memory access operations between the first memory and a second memory. The memory access operations include a main memory access operation for a current processing operation that is performed by the processing unit, and a standby memory access operation for a standby processing operation that is performed by the processing unit after the current processing operation. A level of the first memory is equal to a level of the processing unit, and a level of the second memory is different from the level of the first memory.

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Seongnam-si, South Korea

Kyeongryeol Bong