Samsung Electronics Co., Ltd.

Kyeongjoon Ko

Jaehyun Park

Junhan Bae

Jongjae Ryu

Gyeongseok Song

Hanseok Kim

Nakwon Lee

Youngho Choi

Seuk Son

Hobin Song

Donghyuk Lim

Kangjik Kim

Sooeun Lee

Byeonggyu Park

Sunggeun Kim

Dasom Park

Byunghyun Lim

Byoungjoo Yoo

An integrated circuit is provided. The integrated circuit includes: an active region extending in a first direction; gate electrodes extending in a second direction in parallel with each other; source/drain regions provided on the active region between the gate electrodes; a first gate contact connected to the gate electrodes and extending in the first direction; a first gate wiring pattern provided in a first wiring layer, electrically connected to the gate electrodes through the first gate contact, and overlapping the first gate contact along a third direction perpendicular to the first and second directions; and source/drain wiring patterns provided in a second wiring layer, electrically connected to the source/drain regions, respectively, extending in parallel with the second direction, and overlapping the source/drain regions along the third direction, the second wiring layer being provided on the first wiring layer.

Integrated circuit including high-speed device

A receiver is provided. The receives includes: a signal detection circuit configured to receive differential signals having a variable data rate, and provide a detection signal based on the differential signals corresponding to a first data pattern of a first frequency, wherein the first data pattern of the first frequency indicates an exit from an electrical idle state; an analog-digital converter circuit configured to generate sample data by sampling the differential signals at a second frequency, and identify whether the sample data corresponds to a second data pattern which indicates normal data; and a control circuit configured to enable the analog-digital converter circuit based on the detection signal, and store the sample data. The first frequency is lower than the second frequency.

Receiver, interface circuit including the same, and method of operating receiver

A clock data recovery circuit includes an inphase-quadrature (I-Q) merged phase interpolator circuit configured to generate a first clock pair and a second clock pair from a plurality of reference clock signals, the plurality of reference clock signals having different phases, the first clock pair comprising an I clock signal and an inverted I clock signal, and the second clock pair comprising a Q clock signal and an inverted Q clock signal, a sampler circuit configured to sample input data based on the first clock pair and the second clock pair, and a control circuit configured to control phases of the first clock pair and the second clock pair, the controlling including providing a control signal to the I-Q merged phase interpolator circuit based on a sampling result of the sampler circuit, the I-Q merged phase interpolator circuit is configured to share analog inputs based on the control signal.

Clock data recovery circuit and apparatus including the same

A digital-to-analog converter includes a current cell array including a plurality of current cells, each current cell of the plurality of current cells being configured to generate a current of a same magnitude; a first pattern connecting first current cells, among the plurality of current cells, arranged along a diagonal line of the current cell array; a second pattern connecting second current cells, among the plurality of current cells, arranged along a first oblique line parallel to the diagonal line; and a third pattern connecting third current cells, among the plurality of current cells, arranged along a second oblique line parallel to the diagonal line, the third pattern being electrically connected to the second pattern, wherein the diagonal line is between the first oblique line and the second oblique line.

Digital-to-analog converter including current cell array

A latch circuit and an equalizer including the same are provided. The equalizer includes: an even data path configured to receive a reception data signal and including a first summing circuit and a first latch circuit; and an odd data path configured to receive the reception data signal and including a second summing circuit and a second latch circuit. An even data signal output from the first latch circuit is configured to be input to the second summing circuit, and an odd data signal output from the second latch circuit is configured to be input to the first summing circuit. Each of the first latch circuit and the second latch circuit includes a latch and a multiplexer.

Latch circuit and equalizer including the same

Provided is an equalizer including: an input amplifier configured to amplify and output an input signal; a first equalization circuit including a first sampling circuit, a first arithmetic circuit, and a second arithmetic circuit, the first sampling circuit being configured to generate and output 1-1 to 1-N feedback signals, wherein N is a natural number greater than or equal to 2; and a second equalization circuit including a second sampling circuit, a third arithmetic circuit, and a fourth arithmetic circuit, the second sampling circuit being configured to generate and output 2-1 to 2-M feedback signals, wherein M is a natural number greater than or equal to 2.

Equalizer, operating method of equalizer and system including equalizer

Provided are a summing circuit and an equalizer including the summing circuit. The summing circuit includes: a reference signal generator generating a first reference signal and a second reference signal, based on a coefficient code; a first non-overlap clock buffer generating a first switching signal and a second switching signal by using the first reference signal; and a first current source receiving the first switching signal and the second switching signal generated by the first non-overlap clock buffer, generating a first output current by using a bias voltage, and outputting the first output current to an output line, wherein the first switching signal includes a switching signal and a complementary switching signal that is a complementary signal to the switching signal, and wherein a logic low period of the second switching signal is included in a logic high period of the complementary switching signal of the first switching signal.

Summing circuit and equalizer including the same

A digital-to-analog conversion circuit includes a first digital-to-analog converter (DAC) and a second DAC. The first DAC includes a first current generation circuit (CGC) and a first current-to-voltage converter. The first CGC generates a first current based on a first digital code received through a first terminal to provide the first current to an output node. The second DAC includes a second CGC and a second current-to-voltage converter. The second CGC generates a second current based on a second digital code received through a second input terminal to provide the second current to the output node. The first current-to-voltage converter and the second current-to-voltage converter convert a sum of the first current and the second current to a an analog voltage corresponding to a sum of the first digital code and the second digital code, and output the analog voltage at the output node.

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Yongin-si, South Korea

Kyeongjoon Ko