Gct Semiconductor, Inc.

Silicon Image Gmbh

Osong Medical Innovation Foundation, Korea University Research and Business Foundation

Hl Mando Corporation

Anapass Inc.

Gct Research, Inc.

Samsung Electronics Co., Ltd.

Global Communication Technology Inc.

Kyeongho Lee

Joonbae Park

Deog-Kyoon Jeong

Jeong-Woo Lee

Yido Koo

Seung-wook Lee

Jeong Woo Lee

Eunseok Song

Kang Yoon Lee

Hyungki Huh

Jongsun Park

Eal Wan Lee

Deog-kyoon Jeong

Deog-Kyon Jeong

Wonchan Kim

David D Lee

Woong Il Choi

Sungjoon Kim

Jeongwoo Lee

Yeshik Shin

Su Won Kang

Youngho Ahn

Byoung-Hoon Kim

Won-Seok Lee

Kang-yoon Lee

Hyunjun Kim

Yongsam Moon

Bong Sung Ko

Suwon Kang

Hoe-Sam Jeong

In Ho Song

Bong Youl Cho

Hyunchul Park

Deok Hee Lee

Seung-Wook Lee

Sang Hun Jung

Joonbac Park

Joonban Park

Hei-sam Jeong

Young-Deuk Jeon

Hei-Sam Jeong

The present disclosure provides a driving unit of a steering apparatus configured to provide an auxiliary torque of a steering apparatus and including a driving housing having an installation region formed therein, and the driving unit includes a worm shaft disposed in the installation region and having a worm gear formed therein, a first bearing rotatably supporting one side of the worm shaft, a damper penetrating and supporting one side of the worm shaft supported by the first bearing, and a stopper penetrating and supporting one side of the worm shaft passing through the damper, one end of the stopper being spaced apart from the damper so that a movement of the damper is limited in an axial direction of the worm shaft.

Driving unit of steering apparatus

An SRAM cell includes a first pass gate transistor connected with a first word-line and a local bit-line, a first inverter that includes an output terminal connected with the first pass gate transistor and an input terminal, a second inverter that includes an input terminal connected with the first pass gate transistor and an output terminal, a second pass gate transistor connected with a second word line, the input terminal of the first inverter and the output terminal of the second inverter, and a complementary local bit-line, a first transistor connected with the second pass gate transistor, a local computing line, and a ground electrode, and a second transistor connected with a third word-line, the local computing line, and the ground electrode.

SRAM cell configured to perform multiply-accumulate (MAC) operation on multi-bit data based on charge sharing and method of operating the same

A bearing is disposed between a steering shaft and an inner column covering at least a part of the steering shaft. The bearing includes: an inner ring supporting an outer circumference of the steering shaft and having an elastically deformable material such as a plastic-containing material; an outer ring of which at least a part faces an inner circumference of the inner column; and a roller rotatably disposed between the inner ring and the outer ring. The bearing may be included in a steering apparatus.

Bearing and steering apparatus having the same

Embodiments of the present disclosure described herein relate to a computing in memory electronic device that supports current based analog operations and time based analog-to-digital conversion.

Computing in memory electronic device capable of supporting current based analog multiply-accumulation operations and time based analog-to-digital conversion

The present disclosure is direction to a stopper disposed in a driver for a steering apparatus which includes a worm gear, a bearing supporting rotation of the worm gear, and a damper buffering an impact of the bearing is provided, the stopper including: an annular body having a through hole therein allowing one side of the worm gear to pass through; and a leg on the annular body to protrude toward the damper along an axial direction of the worm gear.

Stopper and driver for steering apparatus having the same

An in-memory computing device includes a memory cell array and a column peripheral circuit including a plurality of column peripheral units connected to a plurality of pairs of bit lines connected to the memory cell array. Each of the column peripheral units includes a sense amplifying and writing unit sensing and amplifying bitwise data through one pair of bit lines among the pairs of bit lines and an arithmetic logic unit performing an arithmetic operation with a full adder Boolean equation based on the bitwise data and performing a write back operation on operation data obtained by the arithmetic operation via the sense amplifying and writing unit.

In-memory computing device supporting arithmetic operations

A computing in-memory device includes a memory cell array supporting a bitwise operation through at least one pair of memory cells activated in response to at least one pair of word line signals and a peripheral circuit connected to the at least one pair of memory cells via one pair of bit lines and performing a discharging operation on at least one bit line of the one pair of bit lines based on a voltage level of the one pair of bit lines.

Computing in-memory device supporting arithmetic operations and method of controlling the same

Embodiments according to the application relates to an OFDM (orthogonal frequency division multiplexing) receiving circuit and methods thereof configured to have a plurality of demodulation paths for an oversampling ADC, which can increase or improve an overall performance of the circuit.

OFDM receiving circuit having multiple demodulation paths using oversampling analog-to-digital converter

The present invention relates to an apparatus and a method for measuring an in phase and quadrature (IQ) imbalance. One embodiment according to the present general inventive concept can provide a method for measuring a Tx IQ imbalance generated in an IQ up-conversion mixer and an Rx IQ imbalance generated in an IQ down-conversion mixer, that includes measuring a first IQ imbalance corresponding to a first combination of the Rx IQ imbalance with the Tx IQ imbalance, measuring a second IQ imbalance corresponding to a second combination of the Rx IQ imbalance with the Tx IQ imbalance and obtaining the Tx IQ imbalance and the Rx IQ imbalance from the first IQ imbalance and the second IQ imbalance.

Apparatus for measuring IQ imbalance

The present general inventive concept relates to apparatuses and/or methods for measuring an in-phase and quadrature (IQ) imbalance. In one embodiment, a detector can measure an error caused by an IQ imbalance using a first IQ signal including a desired signal and a corresponding image signal by the IQ imbalance. The detector can include a derotator to derotate the first IQ signal by a first angular frequency to obtain a second IQ signal and derotate the first IQ signal by a second angular frequency to obtain a third IQ signal, a DC estimator to obtain a fourth IQ signal corresponding to a DC component of the second IQ signal and a fifth IQ signal corresponding to a DC component of the third IQ signal and a controller can determine a gain error or a phase error from the fourth IQ signal and the fifth IQ signal.

Apparatus for measuring in-phase and quadrature (IQ) imbalance

The present general inventive concept relates to apparatuses and/or methods for measuring an in-phase and quadrature (IQ) imbalance. In one embodiment, a signal generator can provide a first IQ signal of a DC component during a first period and the first IQ signal of a first angular frequency during a second period, an IQ up-conversion mixer can up-convert the first IQ signal by a second angular frequency during the first period and up-convert the first IQ signal by a third angular frequency during the second period to output a second IQ signal, an IQ down-conversion mixer can down-convert the second IQ signal by the third angular frequency to output a third IQ signal and an IQ imbalance detector can obtain a first IQ imbalance (e.g., Rx IQ imbalance) from the third IQ signal during the first period and a second IQ imbalance (e.g., Tx/Rx IQ imbalance) during the second period.

An integrated circuit package includes an inductance loop formed from a connection of bonding wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a bonding pad on the integrated circuit chip to an I/O pin of the package and a second wire which connects the same bonding pad to the same pin. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization.

Integrated circuit package having inductance loop formed from same-pin-to-same-bonding-pad structure

Embodiments of a phase lock loop and a method for compensating a temperature thereof can output an initial tuning digital value for a voltage controlled oscillator configured to output a desired phase lock loop frequency compensated according to a temperature change. Embodiments of a phase lock loop and a method for compensating a temperature thereof can simultaneously perform a digital coarse tuning and an analog fine tuning to compensate for a temperature in a limited time.

Phase locked loop and method for compensating temperature thereof

The application discloses embodiments of methods and/or systems for compensating a transmission carrier leakage of an up-conversion mixer, a tranceiving circuit or apparatus embodying the same. One embodiment of a method can include detecting an I channel DC offset DCIand a Q channel DC offset DCQgenerated by a reception carrier leakage from an output of a down-conversion mixer, detecting an I channel DC offset DCI and a Q channel DC offset DCQ from the output of the down-conversion mixer while varying a compensation parameter being inputted to an up-conversion mixer that has its output coupled to an input of the down-conversion mixer to determine the compensation parameter that can reduce or minimize a transmission carrier leakage. A combination of a transmission baseband signal and the determined compensation parameter can be transmitted using the up-conversion mixer and an antenna to compensate for the transmission carrier leakage.

Method for compensating transmission carrier leakage and transceiving circuit embodying the same

Embodiments of an RFIC and methods for same and mobile terminals can internally reduce an input voltage to provide a prescribed voltage to a radio frequency transceiver. Embodiments of an RFIC can have a high efficiency and/or a low noise. In one embodiment, a device can include a PMIC and an RFIC. The RFIC can include an RF transceiver to carry out an RF transmission and an RF reception, a DC-DC converter to lower a voltage provided by the PMIC, and an LDO regulator to regulate the lowered voltage to a fixed voltage used by the RF transceiver.

Radio frequency integrated circuit

Growing community of inventors

Seoul, South Korea

Kyeongho Lee