Electronics and Telecommunications Research Institute

Korea Telecommunication Authority

Kyeong Soo Kim

Hyup Jong Kim

Jeong Jin Lee

Mun Kee Choi

Chan Pak

Keun Bae Kim

A fully-interconnected ATM switching apparatus comprising a plurality of line interface circuits, each of the line interface circuits including an input port driver for extracting an SDH transmission frame containing cell data with a fixed length and a connection identifier from an input signal, appending a routing tag to the extracted SDH transmission frame and outputting the resultant SDH transmission frame through an input dedicated bus and an output port driver for receiving a cell stream from an output dedicated bus, removing the routing tag from the received cell stream, translating a channel identifier in the connection identifier and transferring the resultant SDH transmission frame to an adjacent node, a system clock distributor for generating a clock signal, an initialization controller for controlling system initialization and restart operations, a switch maintenance controller for performing a switch maintenance control operation in response to a network managing cell, a switch call processing controller for performing a call processing operation, a switch module controller for controlling a switching operation, and a plurality of switch output multiplexers for switching cells from the input port drivers to the output port drivers under the control of the switch module controller.

Fully-interconnected asynchronous transfer mode switching apparatus

The present invention relates to an Asynchronous Transfer Mode (ATM) multi-channel switch with a structure of grouping/trap/routing that, by designating a port as a group, could accept not only the services having higher speed than the speed of input ports, but also the services having super-rate speed by comprising: an input processing unit for executing reading control of externally inputted cells and adjusting synchronization between an externally inputted cell and a cell returned by blocking and feedback; a channel grouping unit for grouping cells outputted from the input processing unit, according to switching control data; a trapping unit for deciding whether cells grouped in the channel grouping means require switching beyond the capacity of the pertinent channel and, if these cells require switching beyond the capacity of the channel, sending them to the input processing unit by feedback; and a routing unit for routing cells outputted from the trapping unit.

Asynchronous Transfer Mode (ATM) multi-channel switch with structure of

The present invention relates to a fixed length packet switching apparatus using multiplexers and demultiplexers in which the apparatus has an output buffer-type construction, protects itself from a temporary overflow occurrence of an output terminal and has the construction of the mutual flow control to enhance its entire performance. The present invention can protect the entire operations as well as enhance the entire performance of the switching apparatus by preventing an obstacle of the switching apparatus due to an overflow temporarily generated from an output terminal, process without a loss of excessive cells a traffic phenomenon of one output port in the switching apparatus, reduce the necessary buffer according to the effect of the rate gain and process smoothly input traffic of the internal buffer having a burst characteristic. Further more, the present invention has a duplicate function of cells able to provide a broadcast-type service distributed to subscribers at one time so that the subscribers can receive a distributed service to thereby increase the effectiveness of the channel.

Fixed length packet switching apparatus using multiplexers and

An ATM multiplexing system comprising a plurality of ATM cell input circuits, each of which stores a cell stream incoming from a corresponding input stage and absorbs and removes instantaneous displacement of the incoming cells, a priority encoder for receiving simultaneously FIFO storage level information from the ATM cell input circuits and determining a priority for processing first an input stage with the largest number of stored cells, the FIFO storage level information including the number of the cells stored in the ATM cell input circuits, a link table processing circuit for receiving output headers from the priority encoder and input port numbers corresponding to the received headers and outputting changed headers corresponding to the received headers, an ATM cell output circuit for receiving the changed headers and link information from the link table processing circuit, determining a cell transmission order according to a service priority and performing a header assembling function for perfect cell production, a cell transmission controller for transmitting output headers from the ATM cell output circuit and the corresponding payloads and controlling the above-mentioned components, and a clock signal control circuit for generating a clock signal to control timing of the above-mentioned components.

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Daejeon, South Korea

Kyeong Soo Kim