Samsung Electronics Co., Ltd.

Kye-hyun Kyung

Chang-Sik Yoo

Kee-hoon Lee

Chang-sik Yoo

Byung-sik Moon

Tae-Hyun Kim

Chang Sik Yoo

Byung-se So

Tae-hyun Kim

Byung-sick Moon

Sung-joo Lee

Joon-wan Chai

Kyu-han Han

Sun-byeong Yoon

Hye-In Chol

Dong-hak Seen

An integrated circuit memory device may include a memory cell array and a plurality of data input/output pins. The plurality of data input/output pins may be configured to receive data from a memory controller to be written to the memory cell array during a data write operation, and the data input/output pins may be further configured to provide data to the memory controller from the memory cell array during a data read operation. A mode register may be configured to store information defining an operational characteristic of the memory device, and the mode register may be configured to be set using the data input/output bus. Related methods, systems, and additional devices are also discussed.

Integrated circuit memory devices including mode registers set using a data input/output bus

Example embodiments of the present invention include a memory device testable without using data and a dataless test method. The memory device includes a plurality of registers to store test patterns, the registers being coupled to input/output DQ pads. The test patterns are stored in the registers when a mode register of the memory device is set. The memory device transfers the test patterns to a DQ pad responsive to a write test signal, and transfers the test patterns from the DQ pad to a data input buffer responsive to a read test signal. The memory device writes the test patterns transferred to the data input buffer to memory cells. The memory device reads data stored in the memory cells responsive to the write test signal and transfers the memory cell data from the DQ pad to a comparator responsive to the read test signal. The memory device compares the test patterns to the memory cell data transferred to the comparator and generates an indicator signal to indicate the comparison result.

Memory device testable without using data and dataless test method

A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation. An enable signal may be provided from the memory controller to a second one of the integrated circuit memory devices over a signal line between the memory controller and the second integrated circuit memory device to thereby enable implementation of the mode register set command for the second integrated circuit memory device during the mode register set operation. Moreover, the disable signal may not be provided to the second integrated circuit memory device during the mode register set operation, and the enable signal may not be provided to the first integrated circuit memory device during the mode register set operation. Related systems, devices and additional methods are also discussed.

Integrated circuit memory devices that support selective mode register set commands

Integrated circuit memory devices that support selective mode register set commands and related methods

A method of operating a memory system including a plurality of memory devices coupled to a command address bus may be provided. In particular, a first memory device of the plurality of memory devices may be set to a first operating mode, and a second memory device of the plurality of memory devices may be set to a second operating mode different than the first operating mode. In addition, a read/write operation may be performed responsive to a read/write command address signal provided over the command address bus to the plurality of memory devices so that the first memory device operates according to the first operating mode during the read/write operation and so that the second memory device operates according to the second operating mode during the read/write operation. Related systems are also discussed.

Methods of operating memory systems including memory devices set to different operating modes and related systems

A memory system having a stub-bus configuration transmits a free-running clock through the same path as data signals. A single clock domain is employed for both read and write operations. For both operations, the read or write clock signal is routed through the same transmission path as the data, thereby increasing system transfer rates by maximizing the window of data validity. In this manner, data bus utilization is increased due to the elimination of a need for a preamble interval for the strobe signal, and pin count on the memory module connectors is therefore reduced.

Memory system having stub bus configuration

A memory device includes a control circuit configured to disable a local input/output line sense amplifier responsive to a global input/output line sense amplifier enable signal. The device may further include a column select gate configured to control transfer of data from a memory cell to the local input/output line and the control circuit may be configured to disable transfer of data via the column select gate responsive to the global input/output line sense amplifier enable signal.

Memory devices and methods of operation thereof using interdependent sense amplifier control

Methods of controlling memory modules that support selective mode register set commands

Integrated circuit memory devices that support selective mode register set commands and related memory modules, memory controllers, and methods

A clocking system and method in a point-to-point bus configuration overcomes the limitations of conventional approaches. In one embodiment, the present invention ensures the same phase relationship for the write clock in the write direction for all data transfers between modules, and similarly the same phase relationship for the read clock in the read direction for all data transfers between modules, regardless of module location. In another embodiment, on a given module, all transfers of data between a data buffer and a memory device in both read and write directions are clocked by a read clock signal and a write clock signal that have the same phase relationship and have the same propagation delay as the data bus between the buffer and the memory device.

Memory system having point-to-point bus configuration

An integrated circuit memory device for use in a memory system receives predetermined command/address signals from a memory controller and reads and writes data in response to the command/address signals. The memory device includes at least one input/output terminal that inputs/outputs data from/to the memory controller via a data input/output bus, at least one termination resistor, and an active termination control signal generator that generates a control signal to control active termination of the at least one data input/output terminal in response to a chip selection signal from the memory controller. The memory device also includes at least one switch coupled in series with the at least one termination resistor between the at least one input/output terminal and a predetermined voltage wherein the at least one switch is switched on/off in response to the control signal such that the at least one input/output terminal is connected/disconnected to/from the predetermined voltage responsive to the control signal and such that the at least one termination resistor is coupled in series between the predetermined voltage and the at least one input/output terminal when the at least one switch is switched on and such that the at least one input/output terminal is decoupled from the predetermined voltage when the at least one switch is switched off. Related memory systems and methods are also discussed.

Semiconductor memory systems, methods, and devices for controlling active termination

The semiconductor memory device includes a selecting circuit for selectively changing the mapping of address information to rows of normal and redundant memory cells. By controlling the operation of the selecting circuit, a row of normal memory cells including a defective memory cell can be replaced with an available row of non-defective redundant memory cells even if the row of redundant memory cells is not usually associated with the row of normal memory cells being replaced.

Semiconductor memory device and method of repairing the same

A semiconductor memory device having a mode control circuit includes a mode entrance portion for outputting an output signal in response to an external control signal, a mode entrance control portion for generating a mode entrance enable signal, MDEN, for controlling entry by the semiconductor device into a specific mode, for example a test mode, and a logic portion for combining the two to generate a mode signal for setting the specific mode. The mode entrance control portion includes a first and second fusing portion each including a fuse and a power-up signal for activating the MDEN in a case where the first and second fuses are maintained at an initial state or are changed at the initial state, and deactivating the MDEN otherwise. The mode control circuit prevents improper entry into the specific mode.

Mode control circuit for semiconductor device and semiconductor memory device having the mode control circuit

A memory system and a semiconductor memory device, which are capable of increasing memory bus efficiency and a refresh method of the semiconductor memory device are provided. A method for refreshing an open bank of a semiconductor memory device with a memory controller in a memory system including a plurality of semiconductor memory devices and the memory controller for controlling the plurality of semiconductor memory devices includes (a) applying a refresh command to each of the plurality of semiconductor memory device in order to the open bank; (b) precharging the open bank with each of the plurality of semiconductor memory devices if the refresh command is applied to the each of the plurality of semiconductor memory devices; and (c) refreshing the precharged bank with each of the plurality of semiconductor memory devices. The memory controller does not need to apply a precharge command to the semiconductor memory device before applying a refresh command to the semiconductor memory device but applies only the refresh command to the semiconductor memory device in order to perform a refresh operation on an open bank of the semiconductor memory device. In addition, the semiconductor memory device automatically performs an activation operation on the completely refreshed bank after refreshing the open bank, thereby considerably increasing the efficiency of the memory bus.

Memory system and semiconductor memory device for enhancing bus efficiency and refresh method of the semiconductor memory device

A memory system, which is capable of increasing the utilization efficiency of a semiconductor memory device, and a method of refreshing the semiconductor memory device are provided. The memory controller can selectively perform a refresh operation on a particular bank by applying a refresh command without also applying a bank address, and thus it is possible to increase the utilization efficiency of a semiconductor memory device.

Growing community of inventors

Suwon, South Korea

Kye-hyun Kyung