Samsung Electronics Co., Ltd.

Kye-Hyun Kyung

Dong-jin Lee

Chang-Sik Yoo

Jae-Yong Jeong

Chul-Ho Lee

Bo-Geun Kim

Seok-cheon Kwon

Bong-seok Chae

Seung-Hun Choi

Young-Woo Park

Sung-Il Chang

Jei-Hwan Yoo

Eunsung Seo

Chang Hyun Lee

Chul Bum Kim

Nak-Won Heo

Jin-man Han

Jong-soo Lee

Moo-Sung Chae

Kyu-Han Han

Cheon-An Lee

Dae-sun Kim

Sang-chul Kim

Seok-hun Hyun

Jun-ho Shin

Tae-seek Son

Hyo-jin Oh

A memory system including a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.

Memory system controlling peak current generation for a plurality of memories by synchronizing internal clock of each memory with a processor clock at different times to avoid peak current generation period overlapping

A memory system includes a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.

Memory system controlling peak current generation for a plurality of memories by monitoring a peak signal to synchronize an internal clock of each memory by a processor clock at different times

The present invention relates to a synchronous semiconductor memory device with double data rate, and more particularly, to a synchronous semiconductor memory device for inputting and outputting data using a free-running clock and inserting a preamble indicative of start of data into the outputted data. A semiconductor memory device of the present invention receives a data read command from the exterior of the memory device in response to a predetermined clock signal inputted from the exterior, and outputting data including a preamble in response to the clock signal.

Method for receiving data

Method of writing data to a memory

A semiconductor memory device has a memory cell region and a peripheral region. The device includes low voltage transistors at the peripheral region having gate insulation films with different thicknesses. For example, a gate insulation film of a low voltage transistor used in an input/output circuit of the memory device may be thinner than the gate insulation film of a low voltage transistor used in a core circuit for the memory device. Since low voltage transistors used at an input/output circuit are formed to be different from low voltage transistors used at a core circuit or a high voltage pump circuit, high speed operation and low power consumption characteristics of a non-volatile memory device may be.

Non-volatile memory device with high speed operation and lower power consumption

A termination resistor is mounted on a memory circuit and provides a termination resistance for the memory circuit. The termination resistor includes a node, a plurality of first termination resistors responsive to a corresponding control signal and connected between a power voltage and the node, and a plurality of second termination resistors responsive to a corresponding control signal and connected between a ground voltage and the node.

Devices and methods for controlling active termination resistors in a memory system

A semiconductor memory device includes a plurality of memory areas. Each of the memory areas includes a normal cell array and a redundancy cell array for repairing defective cells generated in the normal cell array such that the semiconductor memory device is usable even when memory arrays include defective cells. A size of a redundancy cell array of a first memory area is greater than a size of the redundancy cell arrays of the other memory areas.

Semiconductor memory devices having redundancy arrays

Semiconductor memory device and module for high frequency operation

Example embodiments relate to a line defect detection circuit, including a first driver disposed at one end of a line and configured to drive the line using a first voltage or a second voltage in response to a control signal, and a second driver disposed at the other end of the line and configured to drive the line using the second voltage in response to a stress signal.

Line defect detection circuit for detecting weak line

A delay locked loop adapted to delay an external clock signal and to output an internal clock signal, the delay locked loop including a renewal signal generator that outputs a renewal signal that is selectively activated and inactivated, a replica path that is active when the renewal signal is activated and is inactive when the renewal signal is inactivated, the replica path delaying the internal clock signal by a delay time of a normal path of a semiconductor device to output a replica internal clock signal when the renewal signal is activated, a control signal generator adapted to vary and to output a delay control signal according to a phase difference between the external and the replica internal clock signals, and a variable delay circuit adapted to delay the external clock signal by a time corresponding to the delay control signal and to output the internal clock signal.

Semiconductor device including delay locked loop having periodically activated replica path

A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.

Synchronous semiconductor memory device having on-die termination circuit and on-die termination method

By using the combination of a pre-existing command signal that is common to two memory devices and a non-shared command signal that is applied individually to each of the devices, embodiments of the invention may operate in a mirror mode, thereby preventing unwanted signal degradation due to stub loads. Because embodiments of the invention do not require additional dedicated pins and/or pads compared to the conventional art, it is possible to achieve mirror mode operation in a smaller device package.

System, device, and method for improved mirror mode operation of a semiconductor memory device

Growing community of inventors

Yongin-si, South Korea

Kye-Hyun Kyung