Samsung Electronics Co., Ltd.

Kye-Hyun Baek

Jin-wook Lee

Sung-il Park

Hong-bae Park

Yong-Ho Jeon

Yong-Jin Kim

Jae-hyun Park

Yoon-Jae Kim

Min-chan Gwak

Hyung-suk Lee

Yun-il Lee

Chang-yeon Lee

Yong-jin Kim

Cheol Kyu Kim

Cheol Jin Kim

Gyung-Jin Min

Geum-jung Seong

Chan-Mi Lee

Sang-Wuk Park

Young-cheul Lee

Ho-ki Lee

An integrated circuit (IC) device includes a first region and a second region adjacent to each other along a first direction on a substrate, fin patterns in each of the first and second regions extending along a second direction perpendicular to the first direction; gate electrodes extending along the first direction and intersecting the fin patterns; and an isolation region between the first and second regions, a bottom of the isolation region having a non-uniform height relative to a bottom of the substrate.

Integrated circuit device and method of forming the same

An integrated circuit device including a substrate; a fin-type active region protruding from the substrate; a gate line intersecting the fin-type active region and covering a top surface and side walls thereof; a gate insulating capping layer covering the gate line; source/drain regions at sides of the gate line on the fin-type active region; first conductive plugs connected to the source/drain regions; a hard mask layer covering the first conductive plugs; and a second conductive plug between the first conductive plugs, the second conductive plug connected to the gate line by passing through the gate insulating capping layer and having a top surface higher than the top surface of each first conductive plug, wherein the hard mask layer protrudes from the first conductive plugs and toward the second conductive plug so that a portion of the hard mask layer overhangs from an edge of the first conductive plugs.

Method of manufacturing an integrated circuit device including a fin-type active region

Integrated circuit device including an overhanging hard mask layer

Provided is an etching system and a method of controlling etching process condition. The etching system includes a light source that irradiates incident light into a target wafer, a light intensity measuring unit that measures light intensity according to the wavelength of interference light generated by interference between reflected light beams from the target wafer, a signal processor that detects a time point at which an extreme value in the intensity is generated when the intensity of interference light varies according to the wavelength, and a controller that compares the extreme value generating time point detected from the signal processor with a reference time point corresponding to the extreme value generating time point and controls a process condition according to the comparison result.

Etching system and method of controlling etching process condition

A method of controlling process distribution of a semiconductor process includes receiving process distribution data representing the process distribution of the semiconductor process, receiving a parameter related to the process distribution, generating a virtual metrology model corresponding to the process distribution based on a relationship between the process distribution data and the parameter, and modifying a process variable affecting the process distribution based on the virtual metrology model.

Method of controlling semiconductor process distribution

Provided are a process-parameter prognostic system for predicting the shape of a semiconductor structure, a semiconductor fabrication apparatus having the process-parameter prognostic system, and a method of using the same. The process-parameter prognostic system may have a process prediction unit and a process-change point corresponding unit. The process prediction unit and the process-change point corresponding unit may obtain predicted parameters using measured parameters of semiconductor structures and sensor parameters of plasmas corresponding to the semiconductor structures.

Method of using process-parameter prognostic system for predicting shape of semiconductor structure

Process-parameter prognostic system for predicting shape of semiconductor structure, semiconductor fabrication apparatus having the system, and method of using the apparatus

Growing community of inventors

Suwon-si, South Korea

Kye-Hyun Baek