Samsung Electronics Co., Ltd.

Kye-Hee Yeom

Hyeong-sun Hong

Sun-Young Park

Chang-Hyun Cho

Hyeon-Woo Jang

Keun-Nam Kim

Soo-ho Shin

Kyu-Pil Lee

Jin-Won Jeong

Makoto Yoshida

Dae-Ik Kim

Yong-il Kim

A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers.

Semiconductor device

Semiconductor device including contact pads

Provided is a semiconductor device having bit line expanding islands, which are formed underneath bit lines to reliably expand and connect the bit lines. The semiconductor device includes: a semiconductor layer in which an isolation region and an active region are defined; an insulating layer, which is formed on the semiconductor layer; a plurality of bit lines, which are formed on the insulating layer; and one or more bit line expanding islands, which are formed inside the insulating layer and are electrically connected to a lower portion of at least one of the plurality of bit lines

Semiconductor device having bit line expanding islands

A semiconductor device, including a semiconductor substrate including isolations defining active regions of the semiconductor substrate, a plurality of buried gate electrodes extending below an upper surface of the semiconductor device, and a plurality of bit lines extending along a first direction over the semiconductor substrate, wherein the plurality of bit lines are connected to corresponding ones of the active regions of the semiconductor substrate, and at least a portion of the bit lines extend along a same and/or substantially same plane as an upper surface of the corresponding active region to which it is connected.

Semiconductor devices including buried gate electrodes and methods of forming semiconductor devices including buried gate electrodes

In a semiconductor device having line type active regions and a method of fabricating the semiconductor device, the semiconductor device includes a device isolation layer which defines the line type active regions in a in a semiconductor substrate. Gate electrodes which are parallel to each other and intersect the line type active regions are disposed over the semiconductor substrate. Here, the gate electrodes include both a device gate electrode and a recessed device isolation gate electrode. Alternatively, each of the gate electrodes is constituted of a device gate electrode and a planar type device isolation gate electrode, and a width of the planar type device isolation gate electrode greater than a width of the device gate electrode.

Semiconductor devices having line type active regions and methods of fabricating the same

A semiconductor device, including a semiconductor substrate including isolations defining active regions of the semiconductor substrate, and a plurality of buried gate electrodes between a pair of the isolations, wherein each of the buried gate electrodes and the isolations includes a conductive layer and a capping layer.

Semiconductor devices including buried gate electrodes and isolation layers and methods of forming semiconductor devices including buried gate electrodes and isolation layers using self aligned double patterning

A semiconductor device, including a semiconductor substrate including isolations defining active regions of the semiconductor substrate, a plurality of buried gate electrodes extending below an upper surface of the active regions of the semiconductor device, a plurality of bit lines extending on the semiconductor substrate along a first direction, a plurality of insulating patterns extending on the semiconductor substrate along a second direction that crosses the first direction, and a plurality of capping patterns extending over the bit lines, wherein the insulating patterns and the capping pattern both include insulating material and at least a portion of corresponding ones of the insulating patterns and the capping patterns are in direct contact with each other.

Semiconductor devices including buried gate electrodes including bitline shoulder attack protection and methods of forming such semiconductor devices

A semiconductor device, and a method of forming the same, includes forming a cell bit line pattern and a peripheral gate pattern on a semiconductor substrate. The cell bit line pattern may be formed on an inactive region adjacent to a cell active region of the semiconductor substrate. The peripheral gate pattern may be disposed on a peripheral active region of the semiconductor substrate. A cell contact plug may be formed between the cell bit line pattern and the cell active region. A peripheral contact plug may be formed on the peripheral active region on a side of the peripheral gate pattern. An insulating layer may be formed to expose top surfaces of the cell bit line pattern, the peripheral gate pattern, and the cell and peripheral contact plugs at substantially the same level.

Semiconductor device and method of forming the same

In a semiconductor device having line type active regions and a method of fabricating the semiconductor device, the semiconductor device includes a device isolation layer which defines the line type active regions in a in a semiconductor substrate. Gate electrodes which are parallel to each other and intersect the line type active regions are disposed over the semiconductor substrate. Here, the gate electrodes include both a device gate electrode and a recessed device isolation gate electrode. Alternatively, each of the gate electrodes is constituted of a device gate electrode and a plan type device isolation gate electrode, and a width of the plan type device isolation gate electrode greater than a width of the device gate electrode.

A method of forming an interconnection line in a semiconductor device includes forming an interlayer insulating layer on an underlying layer having a lower conductive layer, patterning the interlayer insulating layer to form an opening exposing the lower conductive layer, forming an additional material layer conformally on the underlying layer including the opening, anisotropically etching the additional material layer to form an opening spacer covering a sidewall of the opening, performing a wet etch process using the opening spacer as an etch mask, forming a conductive layer pattern in the opening, and performing a heat treatment on the opening spacer.

Method of forming an interconnection line in a semiconductor device

According to the present invention, a conductive pad for a self-aligned direct contact and a self-aligned buried contact is formed of a first pad and a second pad, in twice, wherein the self-aligned direct contact and the self-aligned buried contact connect respectively a bit line/storage electrode to a semiconductor substrate. The first pad and the second pad are formed by combining a reverse active type self-aligned contact (RAT-SAC), a contact type self-aligned contact (CT-SAC), and an epitaxial growth processes. Thus, it is prevented that a shoulder portion of a gate electrode is overetched to create electrical short of pad to gate, a size of a pad is limited to a spacing between gate electrodes, a pad and a semiconductor substrate are not electrically connected each other (not-open), and electrical connection is created by lack of margin between BCs, in case of using only one process selected from a group consisting of the RAT-SAC process, the CT-SAC process, and the epitaxial growth processes.

Method for fabricating conductive pad

A method of forming self-aligned contact holes of a semiconductor device presents bridging from occurring between contacts formed in the holes. First, gate electrode structures are formed on a semiconductor substrate. Next, an interlayer insulating film is formed over the gate electrode structures. The interlayer insulating film is formed by forming a first oxide layer of a reflowable material over the semiconductor substrate and gate electrode structures, planarization etching the first oxide layer until the upper portions of the gate electrode structures are uncovered, and then forming a second oxide layer on the planarized upper surface of the first oxide layer. The second oxide layer is selected to have a wet etch rate that is lower than that of the first oxide layer. Then, the insulating film is etched to form a contact hole between gate electrode structures. Finally, a self-aligned contact electrically connected with the semiconductor substrate is formed by filling the contact hole with conductive material.

Growing community of inventors

Suwon-si, South Korea

Kye-Hee Yeom