International Business Machines Corporation

Kwong-Hon Wong

Chih-Chao Yang

Lawrence Alfred Clevenger

Carl John Radens

Timothy Joseph Dalton

Louis C Hsu

Panayotis Constantinou Andricacos

John Owen Dukovic

Cyprian Emeka Uzoh

Daniel C Edelstein

Kenneth Parker Rodbell

Conal Eugene Murray

Chao-Kun Hu

Wilma Jean Horkans

Jeffrey Louis Hurd

Theodorus E Standaert

Hariklia Deligianni

Lubomyr Taras Romankiw

Matteo Flotta

Kirk G Berridge

Frank A Spera

Harikilia Deligianni

Otto P Schick

Jeffrey S Richter

Helmut R Poweleit

Jose Ordonez

The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.

Modified via bottom structure for reliability enhancement

A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.

Structure and method for MOSFET gate electrode landing pad

A method of making an interconnect which includes providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric and depositing an encasing cap over the extended portion of the interconnect structure.

Interconnect structures with encasing cap and methods of making thereof

A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of CU electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.

Electroplated interconnection structures on integrated circuit chips

A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of Cu electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.

Method of making electroplated interconnection structures on integrated circuit chips

An electroplating cell includes a floor, ceiling, front wall, and back wall forming a box having first and second opposite open ends. A rack for supporting an article to be electroplated is removably positioned vertically to close the first open end and includes a thief laterally surrounding the article to define a cathode. An anode is positioned vertically to close the second open end, with the assembly defining a substantially closed, six-sided inner chamber for receiving an electrolyte therein for electroplating the article. The article and surrounding thief are coextensively aligned with the anode, with the floor, ceiling, front and back walls being effective for guiding electrical current flux between the cathode and the anode. In a preferred embodiment, the cell is disposed as an inner cell inside an outer cell substantially filled with the electrolyte, and a paddle is disposed inside the inner cell for agitating the electrolyte therein. The rack is removable and installable vertically upwardly which allows for automated handling thereof.

Vertical paddle plating cell

Growing community of inventors

Wappingers Falls, NY, United States of America

Kwong-Hon Wong