Samsung Electronics Co., Ltd.

Kwon-Young Choi

Jeong-Young Lee

Bum-Ki Baek

Sang-Ki Kwak

Jong-Soo Yoon

Min-Wook Park

Jun-Hyung Souk

Seung-Taek Lim

Sahng-Ik Jun

Sang-Jin Jeon

Jae-Hong Jeon

Hyang-Shik Kong

Mun-Pyo Hong

Woon-Yong Park

Nam-Seok Roh

Keun-Kyu Song

Won-Joo Kim

Se-Hwan Yu

Jung-Joon Park

Han-Ju Lee

Myung-Jae Park

Young-Joon Rhee

Young-Joo Song

Bong-Joo Kang

Bum-Gee Baek

Young-Mi Tak

Young-Jae Tak

San-Jin Jeon

A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.

Thin film transistor array panel and manufacturing method thereof

Gate lines are formed on a substrate. A gate insulating layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited. A photoresist having thicker first portions on wire areas and thinner second portions on channel areas is formed on the upper film. The upper film on remaining areas are wet-etched, and the lower film and the a-Si layers on the remaining areas are dry-etched along with the second portions of the photoresist. The upper film, the lower film, and the extrinsic a-Si layer on the channel areas are removed. The removal of the upper film and the lower film on the channel areas are performed by wet etching, and the first portions of the photoresist are removed after the removal of the upper film on the channel areas.

Contact structure of semiconductor device, manufacturing method thereof, thin film transistor array panel including contact structure, and manufacturing method thereof

In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. The sidewall of the under-layers for the gate line assembly and the data line assembly is exposed through the contact holes. An IZO-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, subsidiary gate pads, and subsidiary data pads. The pixel electrodes are connected to the sidewall of the drain electrodes, and the subsidiary gate and data pads are connected to the sidewall of the gate and the data pads.

Contact structure of a wires and method manufacturing the same, and thin film transistor substrate including the contact structure and method manufacturing the same

A thin film transistor array panel is provided, which includes a substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer; a plurality of ohmic contacts formed on the semiconductor layer; source and drain electrodes formed on the ohmic contacts; a passivation layer formed on the source and the drain electrodes and having a first contact hole exposing a portion of the drain electrode and an opening exposing a first portion of the semiconductor layer and having edges that coincide with edges of the source and the drain electrodes; and a pixel electrode formed on the passivation layer and contacting the drain electrode through the first contact hole.

A thin film transistor array panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line formed on the substrate and intersecting the first signal line; a thin film transistor including a gate electrode connected to the first signal line and having an edge substantially parallel to the first signal line, a source electrode connected to the second signal line, and a drain electrode overlapping the edge of the gate electrode; and a pixel electrode connected to the drain electrode.

A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

Method of manufacturing a thin film transistor array panel

A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

In a method of manufacturing a liquid crystal display using a divisional exposure for a substrate, an overlapping area at the boundary between adjacent shots is provided and the shots left and right to the boundary are exposed in a way that the areas of the shots gradually decreases and gradually increases, respectively, to reduce the brightness difference due to stitch errors between the two shots. For example, the number of unit stitch areas assigned to the left gradually decreases and the number of unit stitch areas assigned to the right shot gradually increases as it goes to the right along the transverse direction in the stitch area. A unit stitch includes an area obtained by dividing a pixel into at least two parts.

Divisionally exposing an active area in LCD with a plurality of shots

Growing community of inventors

Seoul, South Korea

Kwon-Young Choi