Electronics and Telecommunications Research Institute

Korea Telecommunication Authority

Korea Telecom

Kwon Chul Park

Bhum Cheol Lee

Bong Tae Kim

Eun Chang Choi

Hee Young Jung

Jung Sun Kim

Jae Young Kim

Young Boo Kim

Bheom Soon Joo

Hyun Woo Oh

Moon Kyun Oh

Seok Y Kang

Ji Ha Nah

Hang G Bahk

Bheom C Lee

Provided are a system and a method for providing contents using an open API. A contents storing unit stores at least one contents. An open API unit is common to upper applications on the basis of a wired network interface and provides an API that is a communication function realized as components. A communication capability providing unit combines the API with the contents selected by the contents provider, and adds a communication function to the contents on the basis of usable network resources. The contents providing unit provides contents in which a communication function is added.

System and method for providing digital contents using open API

An apparatus for recovering high speed NRZ (non-return to zero) data is disclosed. A phase-locked loop (PLL) frequency-divides the frequency which is outputted from a voltage-controlled ring oscillator, and therefore, the physical limit of the PLL is not affected. The voltage-controlled ring oscillators are installed separately from the PLL, and the voltage-controlled ring oscillators are synchronized with the PLL in the frequency only. Further, the oscillators are phase-locked to the incoming NRZ data, and two voltage-controlled ring oscillators are enabled/disabled by the binary values of the NRZ data. Therefore, a bit synchronization is realized, and thus, the voltage-controlled ring oscillators are directly controlled by the NRZ data. Consequently, the NRZ data can be recovered up to the frequency band at which the voltage-controlled ring oscillators and a D flip flop operate.

Bit synchronization apparatus for recovering high speed NRZ data

The present invention provides a digital phase alignment which to select the clock whose the transition is occured in the close vicinity of a center of the input data unit interval, the rising transition or falling transition of data are detected, as a result, to generate the synthetic clock retiming data upon detecting the transition of data having a random bit column, the retiming clock is reached in the center of eye pattern of data, compared with a single directional transition is detected.

Digital phase alignment apparatus in consideration of metastability

A modified cyclic line coding apparatus for error detection and frame recovery which generates a n-bit modified cyclic cord-word by use of k redundancy bits and partially scrambles the cyclic redundancy check bits using periodic scramble bits. The apparatus includes a transmitter including a modified cyclic redundancy generator unit for generating redundancy bits, a variable period sampled scrambler unit for partially scrambling the redundancy bits, a timing control unit for generating a timing signal, and a multiplexer unit for multiplexing input cell data in accordance with the timing signal. The apparatus also includes a receiver including a modified cyclic redundancy checker unit for outputting a block synchronization signal and sample bits when a block synchronization is detected, while outputting a synchronization error signal when no block synchronization is detected, a variable period sampled descrambler unit for generating descramble bits in accordance with the sample bits, a timing recovering unit for generating a timing signal, and a demultiplexer unit for demultiplexing the cell data in accordance with the timing signal. The apparatus can use various cell sizes, can stably receive the user information of cell data and can achieve an easy bit timing detection.

Cyclic line coding apparatus for error detection and frame recovery

A voltage controlled ring oscillator having a reduced voltage controlled oscillator (VCO) gain by controlling only the fall time of the period of the VCO using integrated circuits and logic circuits. The VCO includes a mixer/inverter circuit, a logic circuit, a delay/inverter circuit, a first delay circuit, a second delay circuit, and a third delay circuit. The VCO gain is reduced by controlling only one pulse width of the logic level High and one pulse width of the logic level Low of the oscillating period. Furthermore, the VCO can be logically controlled by using a simple logic circuit as a component of the VCO.

Voltage controlled ring oscillator

A high-speed bit synchronizer comprising a phase comparator for detecting a phase relationship between a center of an eye pattern of input NRZ data and a rising transition of a clock pulse from a voltage controlled oscillator (VCO) whenever the input NRZ data makes a transition, a frequency comparator for detecting a frequency relationship between a multiple of a period of the clock pulse from the VCO and a multiple of a period of an external reference clock pulse whenever the external reference clock pulse makes a rising or falling transition, phase and frequency comparator gain limiters for limiting gains of the phase and frequency comparators, respectively, a frequency synchronous signal detector for generating frequency synchronous and asynchronous signals in response to an output of the frequency comparator, a phase difference output controller for controlling the transfer of an output of the phase comparator gain limiter in response to an output of the frequency synchronous signal detector, a low pass filter (integrator) for outputting a voltage of a low frequency component to the VCO in response to an output of the phase difference output controller and an output of the frequency comparator gain limiter, and a frequency-divider for frequency-dividing the clock pulse from the VCO at a desired ratio.

High-speed bit synchronizer with multi-stage control structure

A bit synchronizer for NRZ data wherein a loop gain of a phase locked loop in the bit synchronizer is not varied sensitively to bit pattern and rate of the NRZ data and a voltage control led oscillator in the bit synchronizer oscillates synchronously with a multiple of a frequency of an external reference clock pulse even in the absence of NRZ data transitions or over a wide range of variation of a clock frequency of the voltage controlled oscillator, so that the NRZ data and clock can be recovered stably, According to the invention, the bit synchronizer comprises a phase comparator, a first gain controller, a frequency comparator, a second gain controller, a N-frequency divider, a low pass filter and a voltage controlled oscillator.

Bit synchronizer for NRZ data

A phase comparing and CMI/NRZ decoding apparatus for accomplishing bit synchronization of CMI data by producing rising transition or falling transition of the clock pulse at the center of unit bit interval of incoming CMI data, by use of the clock pulse having a period equivalent to 2 unit bit intervals of CMI data, and for realizing stable decoding of CMI data to NRZ data. This apparatus is implemented by means of a data output means 2, a clock pulse generating means 1 for generating in-phase and inverse-phase pulses, a inter-transitions time interval information output means 3 for outputting information about line interval between the data transition and the clock pulse transition, a reference pulse generating means 4, a falling transition detecting and 3-step half-period shifting means 6, a rising transition detecting and 2-step half-period shifting means 5, a CMI/NRZ decoding circuit 7 and a code violation detecting means 8.

Phase comparing and CMI/NRZ decoding apparatus

The present invention provides a phase detector comprising a driver U1 and D-type flip-flops U2 and U3 which reduces the high frequency component of the jitter in VCO, in analog-fashion operation, enables the use of general purpose logic elements being irrespective of the data bit speed, and enables the application of both analog PLL and digital PLL.

Analog and digital phase detector for bit synchronism

The object of the present invention is to provide a phase detector comprising three D-type flip-flops, which compares the transition phase of retiming clock pulses with the phase of the center of the unit bit interval of received data, produces the compared result in digital fashion to operate irrespective of the data bit speed and in the form of a phase information that is compatible with a digital circuit.

Digital phase detector in an NRZ bit synchronous system

A frequency and phase detection circuit in an NRZ bit synchronous system by simultaneously retiming an NRZ input with an in-phase clock and an inverse-phase clock, respectively. A first frequency and phase difference is extracted by supplying the retimed NRZ with the in-phase clock and the delay-compensated NRZ input to an exclusive OR-gate. A second frequency and phase difference is extracted by supplying the retimed NRZ with the inverse-phase clock and the retimed NRZ with the in-phase clock to another exclusive OR-gate.

Frequency and phase detection circuit in NRZ bit synchronous system

A NRZ/CMI (II) code converter comprising a D-type flip-flop for retiming a series of NRZ data bits received thereto with a clock synchronized therewith, an OR-gate connected to said one output of the D-type flip-flop to compose space bits of a series of said received NRZ data bits and a transmitted clock, and a delay element connected to the output of said OR-gate. The converter also comprises another OR gate connected to a negative output of said D-type flip-flop and another D-type flip-flop having a clock input connected to the output of said OR-gate. These elements function to compose mark bits of a series of the NRZ data bits with clock pulses and to generate two-divided alternative mark bits. An exclusive OR-gate is connected to the output of said another OR-gate and the output of said another D-type flip-flop. In the exclusive OR-gate, mark bits are alternatively generated at the mark bit portions of a series of the NRZ data bits, and clock pulses are composed with a series of the NRZ data bits at the space bit portions of a series of the NRZ data bits. In addition, mark bits and space bits of a series of the NRZ data bits can be independently processed for the same time, in order to generate the CMI (II) code.

NRZ to CMI (II) encoding circuit

A reframe circuit in a synchronous multiplexing device comprising a frame synchronizing pattern detection circuit, a frame pattern bit error detection circuit responsive to a serial data stream from the frame synchronizing pattern detection circuit, an in-frame/out-of-frame state discrimination circuit responsive to the output signal from the frame pattern bit error detection circuit and the output signal from the synchronizing pattern detection circuit, a counter phase synchronizing circuit responsive to the output signal from the in-frame/out-of-frame state discrimination circuit, the output signal from the frame synchronization pattern detection circuit and a reference phase signal, and a counter and timing generation circuit responsive to the operating mode control signal from the counter phase synchronizing circuit.

Growing community of inventors

Daejeon, South Korea

Kwon Chul Park