At&t Bell Laboratories

American Telephone & Telegraph Co., At&t Bell Laboratories

Other

Kwok K Ng

Simon M Sze

William T Lynch

Chien-Shing Pai

Protecting device structures are disclosed for protecting one or more protected nodes of an integrated circuit to be protected against electrostatic discharges (ESD). Typically the integrated circuit includes n channel MOS transistors having terminals connected to the protected nodes. In a specific embodiment, the protecting device structure includes an MOS diode structure having source and drain regions and at least a pair of localized auxiliary region. Each of this pair of localized auxiliary regions has a conductivity type that is opposite from that of the source and drain regions. These localized auxiliary regions are located contiguous with the source and drain regions, respectively, and in the channel between the source and drain regions. The protecting device structure is integrated in the integrated circuit and has a terminal that is connected to a terminal of each of the one or more protected nodes of the integrated circuit.

Electrostatic protection devices for protecting semiconductor integrated

In order to reduce the rate of (hot charge-carrier) degradation of semiconductor devices formed in a semiconductor body, a neutral impurity--such as germanium in silicon MOS transistors--is introduced into the body in a neighborhood of an intersection of a p-n junction with a surface of the body.

Neutral impurities to increase lifetime of operation of semiconductor

A test circuit is described for measuring the specific contact resistivity r.sub.c of self-aligned electrodes contacting underlying diffused regions at a major surface of an underlying semiconductor wafer, as well as the sheet (lateral) resistance r.sub.s of the underlying diffused regions in some embodiments. The test circuit illustratively includes a pair of test MOS or other type of transistors advantageously made by a self-aligned metallization process simultaneously with the other MOS or other type of transistors to be tested. The two test transistors share a common diffused region, a self-aligned common controlled electrode contacting a diffused region underneath it, and a common control electrode. During test operation, both est transistors are kept ON by means of an applied above-threshold control voltage, while a current source forces current through one of the transistors. The resulting voltage, developed across the common controlled electrode and the controlled electrode of the other transistor is a measure of the specific contact resistivity thereat.

Test circuit for measuring specific contact resistivity of self-aligned

A new SOI device which permits both the kink effect to be avoided and threshold voltage to be regulated, as well as a new method for fabricating SOI ICs, is disclosed. The new device included an electrically conductive pathway extending from the active volume and terminating in a non-active region of the substrate of the device. A back-gate bias is communicated to, and kink-inducing charges are conducted away from, the active volume through the conductive pathway. The new fabrication methd permits SOI ICs to be fabricated using available circuit designs and pattern delineating apparatus, e.g., IC mask sets. This method involves the formation of a precursor substrate surface which includes islands of insulating material, each of which is encircled by a crystallization seeding area of substantially single crystal semiconductor material. The boundaries of the islands are defined with a first pattern delineating device, e.g., a mask, which, in terms of the pattern it produces, is substantially identical to a second pattern delineating device. The latter device is a component of pattern delineating apparatus used in forming an IC, e.g., an IC mask set, the component being used to delineate the device regions of the IC. A layer of non-single crystal semiconductor material is formed on the precursor substrate surface, and crystallized with little or no displacement of the islands. The pattern delineating apparatus is then used to form an IC in the crystallized material.

Semiconductor-on-insulator (SOI) devices and SOI IC fabrication method

One or more silicon-integrated-circuit chips are attached, active side up, to the top side of a silicon wafer. The top side of the wafer and all but peripheral portions of the attached chip(s) are then coated with an etch-resistant layer. Subsequently, the chips are etched to form sloped edges between the active areas of the chips and the top side of the wafer. A lithographically defined conductive pattern is then formed on the top side of the wafer and on the sloped edges to connect conductive pads on each chip to conductive pads on other chips and/or to conductive terminals disposed along the periphery of the wafer. In other embodiments, at least one chip of the type described is attached to each side of a wafer. In such embodiments, connections can also be made through vias in the wafer to selectively interconnect pads and/or terminals included on both sides of the wafer. The resulting packaged chip assembly has advantageous performance and cost characteristics.

Packaging microminiature devices

One or more silicon-integrated-circuit chips are attached, active side up, to the bottom side of a silicon wafer. A sloped-wall through-aperture is etched in the wafer in registry with a portion of the active side of each attached chip. A lithographically defined conductive pattern is then formed on the top side of the wafer and on the sloped walls to connect conductive pads on each chip to conductive pads on other chips and/or to conductive terminals disposed along the periphery of the wafer. The resulting packaged chip assembly has advantageous performance and cost characteristics.

Growing community of inventors

Berkeley Heights, NJ, United States of America

Kwok K Ng