Lsi Logic Corporation

Texas Instruments Corporation

Njr Corporation

Kwok K Chau

Toshiaki Yoshino

Qiong Wu

David R Auld

Ashwin H Shah

Srinivasa Rao Malladi

James D Gallia

Marc A Miller

Hau-Yung Chen

A method and apparatus is provided for generating various binary addresses for use in decoding MPEG video data. One or more n-bit counters and mutiplexers are used to generate such binary addresses. Different binary addresses can be generated by the same n-bit counter by swapping the bits of the n-bit counter. The number of different binary addresses that an n-bit counter can generate is n factorial.

Unified memory address generation system and method for fetching and storing MPEG video data

A decoder is disclosed that provides dynamic pipelining of an incoming compressed bitstream. The decoder includes decoding logic modules capable of decoding an incoming compressed bitstream, and memory storing logic in communication with at least one of the decoding modules. Preferably, the memory storing logic is capable of determining whether a memory operation is complete that stores the uncompressed video data to memory. In addition, the decoder includes halting logic in communication with the decoding logic and the memory storing logic. The halting logic halts the decoding of the incoming bitstream during a specific time period, which includes a time period wherein the memory operation is incomplete. Finally, initiating logic is included in the decoder that is in communication with the decoding logic and the memory storing logic. The initiating logic of the decoder restarts the decoding when the memory operation is complete.

Method and apparatus for dynamic pipelining

A decoder for decoding a compressed incoming interruptible bitstream is disclosed. The decoder includes an input register that is capable of receiving a latch command, and that is further capable of latching stored data in a particular state upon receiving the latch command. The decoder also includes decoding logic, such as variable length decoding logic, or run-length decoding logic, in communication with the input register. Further included in the decoder is an output register in communication with decoding logic, that is also capable of receiving the latch command, and that is further capable of latching stored data in a particular state upon receiving the latch command. Finally, the decoder includes a register controller in communication with both the input register and the output register. The register controller is capable of receiving a halt command from the system and, upon receiving the halt command, the register controller sends the latch command to both the input register and the output register.

Method and apparatus for bitstream decoding

An MPEG decoder system and method for performing video decoding or decompression which includes a unified memory for multiple functions according to the present invention. The video decoding system includes transport logic, a system controller, and MPEG decoder logic. The video decoding system of the present invention includes a single unified memory which stores code and data for the transport, system controller and MPEG decoder functions. The single unified memory is preferably a 16 Mbit memory. The MPEG decoder logic includes a memory controller which couples to the single unified memory, and each of the transport logic, system controller and MPEG decoder logic access the single unified memory through the memory controller. The video decoding system implements various frame memory saving schemes, such as compression or dynamic allocation, to more efficiently use the memory. In one embodiment, the memory is not required to store reconstructed frame data during B-frame reconstruction, thus considerably reducing the required amount of memory for this function. Alternatively, the memory is only required to store a portion of the reconstructed frame data. In addition, these savings in memory allow portions of the memory to also be used for transport and system controller functions. The present invention thus provides a video decoding system with reduced memory requirements.

MPEG decoder system and method having a unified memory for transport

An MPEG decoder system and method for decoding frames of a video sequence. The MPEG decoder includes frame reconstruction or decoder logic which operates to reconstruct a bi-directionally encoded (B) frame with minimal memory requirements. The MPEG decoder operates to decode or reconstruct the frame twice, once during each field display period. The picture reconstruction unit operates to decode or reconstruct the B frame twice, once each during a first field time and a second field time. The first field time substantially corresponds to the time when the first or top field of the picture is displayed, and the second field time substantially corresponds to the time when the second or bottom field of the picture is displayed. This obviates the necessity of storing the reconstructed B frame data, thus reducing memory requirements. The present invention also eliminates the storage requirement of the B-frame without substantially increasing the bandwidth required from external semiconductor memory when compared to prior art methods.

Method and apparatus for decoding B frames in video codecs with minimal

Disclosed is a partitioning procedure for designing MPEG decoders, AC-3 decoders, and decoders for other audio/video standards. The procedure provides that some specified decoding functionality be implemented exclusively in the form of hardware and certain other specified decoding functionality be provided exclusively as firmware or software. A video decoder designed according to this procedure includes the following elements: (a) firmware or software for implementing, in conjunction with a CPU, video header processing functions; and (b) hardware for implementing preparsing assist, macroblock reconstruction, and video display control functions. An audio decoder designed according to this procedure includes the following elements: (a) firmware or software for implementing, in conjunction with a CPU, decoding fields containing parameters for processing the audio data; and (b) hardware for implementing matrixing and windowing functions on the audio data.

Method for partitioning hardware and firmware tasks in digital

A control system operates in a pipelined mode for executing multiple clock cycle instructions and in an open loop mode for executing single clock cycle instructions. A plurality of electrical functional units are capable of executing single clock cycle instructions and multiple clock cycle instructions that are individually addressed and applied thereto by a processor. The functional units generate current operational statuses after each clock cycle. A status indicator applies new operational statuses of the functional units to the processor. A status memory stores previous operational statuses of the functional units. A control unit controls the status indicator to apply the previous operational statuses to the processor as the new operational statuses after one of the single clock cycle instructions has been applied to the functional units. The control unit further controls the status indicator to apply the current operational statuses to the processor as the new operational statuses after one of the multiple clock cycle instructions has been applied to the functional units. In this manner, the single cycle instructions do not go through the pipeline, and their propagation times are not limited by the pipeline latency.

Soft programmable single-cycle/pipelined micro-programmed control system

A Motion Picture Experts Group (MPEG) video/audio data bitstream includes macroblocks of video data which can each include input Motion Compensation (M) data and input discrete cosine Transform Coded (I) data. A motion pipeline processes the input M data to produce processed M data, and a transform pipeline processes the input I data to produce processed I data. A controller controls the motion pipeline and the transform pipeline to concurrently process the input M data and the input I data respectively such that a length of time required for processing each macroblock is variable and is determined by the largest of a length of time required for the motion pipeline to process the input M data and a length of time required for the transform pipeline to process the input I data of the macroblock. The time required to process all of the macroblocks in a video picture is statistically less than if a fixed length of time were provided for processing each macroblock based on a worst case scenario, thereby reducing the memory bandwidth requirement of the system.

Statistically derived method and system for decoding MPEG motion

A tri-state driver circuit is disclosed which provides rail-to-rail output swings and does not consume a significant amount of d.c. power.

BICMOS tri-state circuit with full output voltage swing

BiCMOS circuits are disclosed which achieve high speed operation under a wide range of loading conditions. The circuits are capable of providing a full output voltage swing and dissipate virtually no static power. The BiCMOS circuits are implemented using both CMOS and bipolar transistors. The circuits use their output signal to control the CMOS transistors that overcome bipolar output drops for full swing operation. The same fundamental CMOS and bipolar configurations can be applied to implement complex and simple logic functions such as NAND, NOR, AND, or OR operations.

High performance BiCMOS logic circuits with full output voltage swing up

An N-bit conditional sum adder 8 includes first and second conditional sum adders 10a and 10b. Each of the adders may be built from a plurality of one-bit conditional sum adders 110. In one embodiment, each one-bit adder 110 comprises a XNOR gate 50, a XOR gate 52, a NAND gate 54 and a NOR gate 56. The carry outputs CO.sub.a and CO.sub.b of the first conditional sum adder 10.sub.a are coupled to BiCMOS drivers 12 and 14 which in turn are coupled to the select inputs of a plurality of multiplexers 16 and 18. The multiplexers may be CMOS multiplexers built from transmission gates.

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Los Altos, CA, United States of America

Kwok K Chau