Samsung Display Co., Ltd.

Samsung Displayco., Ltd.

Kwihyun Kim

Dongwoo Kim

Sang Yong No

Sangyong No

Yeonkyung Kim

Jiho Moon

Keebum Park

Yoon-Jang Kim

Junghwan Hwang

Jongjae Lee

Sungryul Kim

Youngsoo Sohn

Yunseok Lee

Hongmin Yoon

Jongdo Keum

Yoonsik Park

Hwa-Rang Lee

Jiyeon Choi

A pixel circuit includes a light emitting element, a first transistor that applies a driving current to the light emitting element, a second transistor that writes a data voltage in response to a write gate signal, a first capacitor connected to a control electrode of the first transistor, a second capacitor including a first electrode connected to the second transistor and a second electrode connected to the control electrode of the first transistor, a third transistor that diode-connects the first transistor in response to a compensation gate signal, a fourth transistor that applies an initialization voltage to the control electrode of the first transistor in response to a first initialization gate signal, and a fifth transistor that transmits the driving current to the light emitting element in response to an emission signal.

Pixel circuit and display device including the same

A pixel circuit is disclosed that includes first through sixth transistors, first and second capacitors, and a light emitting element. A gate electrode of the second transistor receives a first gate signal. A gate electrode of the third transistor receive a second gate signal. Gate electrodes of each of the fourth and fifth transistors receive a third gate signal. A gate electrode of the sixth transistor receives an emission signal. First electrodes of the first transistor and the first capacitor each receive a first power supply voltage. A cathode electrode of the light emitting element receives a second power supply voltage. A first electrode of the fourth transistor receives an initialization voltage.

A scan driver includes active stages. Each active stage includes a first transistor that resets a control node, a second transistor that transfers a previous carry signal to the control node, a third transistor that transfers a scan clock signal to a scan output node, a first capacitor electrically connected between the control node and the scan output node, a fourth transistor that transfers a first low voltage to the scan output node, a fifth transistor that transfers a carry clock signal to a carry output node, a sixth transistor that electrically connects the control node to the carry output node, and a seventh transistor that transfers a second low voltage to the control node.

Scan driver and display device

A liquid crystal display device includes a liquid crystal layer between first and second substrate. The first substrate includes a first and second sub-pixel areas. A first sub-pixel electrode is on the first substrate in the first sub-pixel area, and a first transistor is connected to a gate line, data line, and first sub-pixel electrode on the first substrate. A second sub-pixel electrode is on the first substrate in the second sub-pixel area, and a second transistor is connected to the gate line, the first transistor, and the second sub-pixel electrode. A first storage line is adjacent to one side of the first sub-pixel electrode. A second storage line is spaced from the first storage line and is adjacent to one side of the second sub-pixel electrode. A third transistor is connected to the gate line, second transistor, and second storage line.

Liquid crystal display device

A display apparatus includes a first substrate, a first dummy substrate on the first substrate, and a second dummy substrate extending from the first dummy substrate and bent. The second dummy substrate is on different side surfaces of the first substrate in a first direction. The display apparatus also includes a plurality of pixels on the first dummy substrate, a gate driver on the second dummy substrate and connected to the pixels, and a data driver connected to one side of the first dummy substrate in a second direction crossing the first direction and connected to the pixels.

Display apparatus, method for manufacturing the same, and multi display apparatus

Deterioration of image quality in a display device due to kickback voltages may be reduced or prevented by varying parasite capacitance, the size of the semiconductor layer, and/or storage capacitance in each of thin film transistors for the pixels in the display. Various embodiments of display devices capable of reducing or preventing kickback voltages are disclosed.

Display device

A display apparatus includes a timing controller, a data driver and a display panel. The data driver generates a positive polarity data voltage and a negative polarity data voltage based on image data compensated by the timing controller. The display panel includes a first pixel driven based on the positive polarity voltage and a second pixel driven based on the negative polarity voltage. The display panel receives a storage voltage applied to the first pixel and the second pixel. The timing controller compensates the image data when a variation on a level of the storage voltage occurs. The compensation shifts a level of the first data voltage from a first normal level to a first compensation level in a direction, and shifts a level of the second data voltage from a second normal level to a second compensation level in the same direction.

Growing community of inventors

Yongin-si, South Korea

Kwihyun Kim