Samsung Electronics Co., Ltd.

Kwi-Sung Yoo

Wun-Ki Jung

Min-ho Kwon

Seog-Heon Ham

Seung-hyun Lim

Dong-Hun Lee

Jae-Hong Kim

Yu-Jin Park

Jin-Ho Seo

Won-Ho Choi

Chi-Ho Hwang

Sang-min Lee

Young-min Choi

Shuichi Shimokawa

Yong Kyun Lim

Dong-min Kim

Kyoung-Min Koh

Jae-Youl Lee

Takafumi Usui

Woo-Seok Choi

Dong-hoon Baek

Hyun-Wook Lim

Eun-young Jin

Kang-sun Lee

Sung-Ho Suh

Kyong-ho Kim

Seung-Hyun Lim

Woo-seok Choi

Beoung-ouk Min

Han-Kook Cho

Min-Ji Hwang

Beoung-Ouk Min

A method of operating a receiver includes a controller of the receiver determining whether a full initialization or a partial initialization of the receiver is needed; the controller adjusting alternating current (AC) characteristics and direct current (DC) characteristics of the receiver in a full initialization mode, and the controller adjusting the DC characteristics of the receiver in a partial initialization mode when the controller determines the partial initialization is needed.

Operating method of receiver, source driver and display driving circuit including the same

A line memory device includes a plurality of memory cells, a data line pair, a sense amplifier and an output unit. The plurality of memory cells are disposed adjacent to each other in a line. The data line pair is coupled to the memory cells to sequentially transfer memory data bits stored in the memory cells to the sense amplifier. The sense amplifier is configured to amplify the memory data bits that are sequentially transferred through the data line pair by corresponding delay times which are different from each other. The output unit samples an output of the sense amplifier to sequentially output retimed data bits of the memory data bits in response to a read clock signal. The read clock signal has a cyclic period which is less than a maximum delay time among the delay times.

Line memory device and image sensor including the same

A solid-state image sensor of an electronic device includes a plurality of pixels arranged in a matrix form and having a plurality of phase difference pixel of the plurality of pixels. The plurality of phase difference pixels are arranged at locations of pixels that are commonly read out in a plurality of different skip readout modes.

Solid-state image sensor, electronic device, and auto focusing method

An image sensor includes a pixel array and an analog-to-digital (A/D) conversion unit. The pixel array generates an analog signal by sensing an incident light. The A/D conversion unit generates a digital signal in a first operation mode by performing a sigma-delta A/D conversion and a cyclic A/D conversion with respect to the analog signal and generates the digital signal in a second operation mode by performing a single-slope A/D conversion with respect to the analog signal. The image sensor provides a high-quality image in a still image photography mode and a dynamic image video mode.

Image sensor and computing system having the same

An image sensor includes a pixel array and a plurality of pairs of column lines. The pixel array includes a plurality of unit pixel areas arranged in a plurality of rows and columns. Each of the unit pixel areas includes a readout circuit connected to a corresponding pair of column lines, and first and second photo-electric conversion devices sharing the readout circuit. Each of the unit pixel areas is configured to output a first pixel signal corresponding to a photoelectron generated by the first photo-electric conversion device through the first column line, and to output a second pixel signal corresponding to a photoelectron generated by the second photo-electric conversion device through the second column line.

Unit pixels configured to output different pixel signals through different lines and image sensors including the same

An analog to digital converter (ADC) can include a multi-input comparison unit configured to compare a pixel voltage from an image sensor, a comparison voltage comprising a stepped voltage modified during a coarse mode of operation, and a ramp voltage comprising a ramped voltage modified to one another during a fine mode of operation, to provide a comparison result signal that indicates whether the comparison voltage combined with the ramp voltage is greater than or less than the pixel voltage. A selection control signal generation unit can receive the comparison result signal and a mode control signal, to indicate the coarse or fine mode, to provide a selection control signal allowing modification of the comparison voltage in the coarse mode and to hold the comparison voltage constant in the fine mode. A reference voltage selection unit can receive the selection control signal to control modification of the comparison voltage.

Analog to digital converters, image sensor systems, and methods of operating the same

An analog-to-digital converter includes a modulation unit and a digital signal generation unit. The modulation unit is disposed corresponding to at least one column line, and sequentially perform delta-sigma modulation on an analog input signal and at least one residue voltage to generate digital bit stream signals. The analog input signal is input through the at least one column line. The at least one residue voltage is generated by performing the delta-sigma modulation on the analog input signal. The digital signal generation unit generates a digital signal corresponding to the analog input signal based on the digital bit stream signals.

Analog-to-digital converter and image sensor including the same

An offset canceling circuit stores charge corresponding to a voltage difference between a reset voltage received from a unit pixel and a reference voltage, thereby canceling an offset of the unit pixel.

Offset canceling circuit, sampling circuit and image sensor

An analog-to-digital converter includes a comparison signal generation unit and a control unit. The comparison signal generation unit determines a logic level of a comparison signal by comparing an input signal with a selected reference signal based on a switch control signal in a first comparison mode, and by comparing a difference voltage with a ramp signal based on the switch control signal in a second comparison mode. The difference voltage is generated based on the input signal and the selected reference signal such that a level of the difference voltage is lower than a fine voltage level corresponding to a voltage level of the selected reference signal in the second comparison mode. The control unit generates the switch control signal based on the comparison signal and a mode selection signal.

Analog-to-digital converter having a comparison signal generation unit and image sensor including the same

Provided are a pixel sensor array and a complementary metal-oxide semiconductor (CMOS) image sensor including the same. The pixel sensor array includes a photoelectric transformation element configured to generate electric charges in response to incident light. A signal transmitting circuit is configured to output the electric charges accumulated in the photoelectric transformation element to a first node based on a first control signal, change an electric potential of the first node to an electric potential of a second signal line based on a second control signal, and output a signal sensed in the first node to a first signal line based on a third control signal. A switch element is configured to connect a supply power terminal to the second signal line based on a fourth control signal. A comparator connected to the first signal line and the second signal line and configured to compare a voltage of the signal and a voltage of a reference signal.

Pixel sensor array including comparator and image sensor including the same

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Seoul, South Korea

Kwi-Sung Yoo