Samsung Electronics Co., Ltd.

Kwi Sung Yoo

Seog Heon Ham

Min Ho Kwon

Dong Hun Lee

Wun-Ki Jung

Jae Hong Kim

Jin Ho Seo

Seung Hyun Lim

Yu Jin Park

Eun Young Jin

Jae Jin Jung

Hyunwook Lim

Seung Jin Lee

Han Vit Yang

Yong Kyun Lim

Kyoung Min Koh

Jeong Heum Lee

Gunhee Han

Jaeyoul Lee

Dong-hoon Baek

Jae Cheol Yun

Jae Youl Lee

Eun-young Jin

Youngmin Choi

Kyongho Kim

Sung Ho Suh

Han Kook Cho

Hyun Wook Lim

Jaejin Jung

Jeonghwan Lee

Dong Hoon Baek

Gun Hee Han

Wontak Choi

Won Ho Choi

Min Ji Hwang

Wun Ki Jung

Soon Hwa Kang

Kun Hee Cho

Dong Myung Lee

An electronic device includes a pixel array that outputs a raw image including color pixels and specific pixels, a logic circuit that outputs a first binned image by performing first binning on pixels in a row direction for each unit kernel of the raw image, and a processor that outputs a second binned image by performing second binning on the first binned image. When a unit kernel includes at least one of the specific pixels, a column to which the at least one specific pixel belongs is read out at a readout timing different from a readout timing of a column to which none of the specific pixels belong and undergoes the first binning. The second binning combines a third binned image of the column to which none of the specific pixels belong with a fourth binned image of the column to which the at least one specific pixel belongs.

Electronic device and image binning method thereof

An image sensor includes a first unit pixel including a first sub-pixel and a second sub-pixel, a second unit pixel including a third sub-pixel and a fourth sub-pixel, a timing controller configured to apply a first effective integration time to the first sub-pixel and the fourth sub-pixel, such that a first sensing signal and a fourth sensing signal are generated from the first sub-pixel and the fourth sub-pixel, respectively, and to apply a second effective integration time shorter than the first effective integration time to the second sub-pixel and the third sub-pixel, such that a second sensing signal and a third sensing signal are generated from the second sub-pixel and the third sub-pixel, respectively, and an analog-to-digital converter configured to perform an averaging operation on the first sensing signal and the fourth sensing signal or on the second sensing signal and the third sensing signal.

Image sensor and driving method thereof

An image sensor includes a pixel array configured to generate a plurality of pixel signals, an analog to digital converter circuit coupled to the pixel array and configured to generate respective digital codes responsive to respective ones of the pixel signals, a plurality of memories, respective ones of which are configured to store respective bits of the digital codes, a signal processing circuit coupled to a plurality of memories and configured to generate analog signals responsive to the stored bits, each of the analog signals corresponding to multiple ones of the stored bits, and a comparator circuit configured to compare the analog signals to respective ones of a plurality of reference signals to generate digital signals corresponding to the multiple ones of the stored bits. Related image processing systems and methods are also described.

Image sensors and image processing systems using multilevel signaling techniques

A display device includes a data generator configured to generate a clock-embedded data packet, and a controller configured to control operation of the data generator. The data packet comprises a header, a first symbol comprising address information therein, and a second symbol not comprising address information, and the header comprises address information of the first symbol.

Display device

A clock and data recovery circuit in accordance with an embodiment of the inventive concept includes a phase locked loop configured to receive a data stream into which an additional bit is inserted at every reference period to generate parallelized data and a clock signal, and a first detector circuit configured to determine whether the parallelized data is locked based on a bit-conversion of the data stream according to an insertion of the additional bit. The bit-conversion is executed with respect to the additional bits according to a predetermined protocol, or is executed with respect to at least one bit from among data of the data stream between a current one of the additional bits and a next one of the additional bits.

Clock and data recovery circuit detecting unlock of output of phase locked loop

An image sensor includes a first column pair and a second column pair among a plurality of columns of a pixel array, an analog-to-digital converter pair, and a switch arrangement circuit configured to connect the first column pair with the analog-to-digital converter pair in response to first switch control signals such that two rows among a plurality of rows in the pixel array are read during a single access time.

Image sensor and system including the same

An analog-to-digital converter includes a gain amplification unit configured to receive a pixel signal at a first node and to amplify a gain of the pixel signal, a first capacitor connected between the first node and a second node, an amplifier configured to receive and amplify a signal output from the gain amplification unit and the first capacitor, and a conversion circuit configured to convert an output signal of the amplifier to a digital signal based on a reference signal and output the digital signal as a first output signal.

Analog-to-digital converter, image sensor including the same, and image processing device including the image sensor

An apparatus includes an operational amplifier circuit comprising at least one operational amplifier and a feedback circuit coupled between the output terminal and input terminal of the operational amplifier circuit and configured to apply a feedback gain to an output signal at the output of the first operational amplifier. The apparatus further includes a variable compensation capacitor coupled to the output terminal of the operational amplifier circuit and configured to vary a capacitance thereof responsive to the feedback gain.

Amplifier apparatus and methods using variable capacitance dependent on feedback gain

A programmable gain amplifier includes a sampling circuit, a source follower, a first capacitor and an error amplifier. The sampling circuit is configured to perform correlated double sampling on an input signal using a reference voltage. The first capacitor is connected between the sampling circuit and the source follower. The error amplifier is connected between an input terminal of the source follower and an output terminal of the source follower. The error amplifier is configured to reset a voltage of the output terminal of the source follower to the reference voltage during a source follower reset operation.

Programmable gain amplifier and devices including the same

An image sensor includes a pixel array including a plurality of pixels which are arranged in a matrix of a plurality of rows and columns and each of the plurality of pixels being configured to convert intensity of incident light into an electrical image signal; and an extended counting analog-to-digital converter configured to perform a first analog-to-digital conversion to provide a digital signal from an output signal of the pixel array, to obtain a residue using the output signal of the pixel array and the digital signal, and to perform a second analog-to-digital conversion using the residue.

Analog-to-digital converters and related image sensors

A two-step analog-digital converting circuit includes a comparator, an upper bit counter and a pulse residue conversion unit. The comparator is configured to compare a ramp signal and an input signal, and to output a resulting comparative signal. The upper bit counter is configured to receive the comparative signal and a clock signal, and to output upper bit values corresponding to a first time interval between a generation time point of the ramp signal and a first edge of the clock signal, the first edge of the clock signal immediately preceding a state transition time point of the comparative signal. The pulse residue conversion unit is configured to receive the comparative signal and the clock signal, and to output lower bit values corresponding to a second time interval between the first edge of the clock signal and the state transition time point of the comparative signal.

Two-step analog-digital converting circuit and method

A sense amplifier having a negative capacitance circuit receives differential input signals via a pair of data lines, and senses and amplifies a voltage difference between differential output signals corresponding to the differential input signals as loaded by the negative capacitance circuit using a differential-to-single-ended amplifier to generate a corresponding data output signal.

Sense amplifier including negative capacitance circuit and apparatuses including same

A correlated double sampling circuit includes a delta-sigma modulator, a selection circuit, and an accumulation circuit. The delta-sigma modulator is configured to receive an input signal, delta-sigma modulate the input signal, and output a modulation signal. The selection circuit is configured to invert the modulation signal and selectively output one of the modulation signal and an inverted modulation signal in response to a selection signal corresponding to an operation phase. The accumulation circuit is configured to generate a first accumulation result by performing an accumulation process on one of the modulation signal and the inverted modulation signal in a first operation phase, and generate a second accumulation result by performing the accumulation process on the first accumulation result and the other one of the modulation signal and the inverted modulation signal in a second operation phase.

Correlated double sampling circuit and image sensor including the same

An image sensor comprises a plurality of pixel units connected to a column line, a signal process circuit configured to process a signal output from the column line according to a switching operation, and a kick-back noise blocking circuit configured to reduce kick-back noise caused by the switching operation. Each of the pixel units includes a photoelectric conversion element. The kick-back noise blocking circuit is connected between the column line and the signal process circuit.

Growing community of inventors

Seoul, South Korea

Kwi Sung Yoo