Electronics and Telecommunications Research Institute

Korea Advanced Institute of Science and Technology

Kwi Dong Kim

Jong Dae Kim

Jong Kee Kwon

Chong Ki Kwon

Hui Dong Lee

Young Deuk Jeon

Seung Chul Lee

Seok Ju Yun

Byoung Gon Yu

Young Kyun Cho

Jong-Kee Kwon

Sang Heung Lee

Ja Yol Lee

Seong Mok Cho

Kyung Soo Kim

Kyoung Ik Cho

Sung Min Yoon

Sang Gug Lee

In Kyu You

Nam Yeal Lee

Min Hyung Cho

Sang Hyun Cho

Yi Gyeong Kim

Seung Tak Ryu

Sang-Hyun Cho

Sangouk Ryu

Sang Ouk Ryu

Yong Seo Koo

Jong Pil Hong

Provided is a spread spectrum clock generating circuit. The spread spectrum clock generating circuit includes: a phase detector receiving a reference frequency signal from the external and detecting a phase difference between the reference frequency signal and a frequency-divided signal; a voltage controlled oscillator outputting an oscillation signal corresponding to a detection result of the phase detector; a main divider generating the frequency-divided signal by dividing a frequency of the oscillation signal by a main dividing ratio; and a dividing ratio controller generating a variable count value, generating a sub dividing ratio by performing delta-sigma modulation according to the count value, and adjusting the main dividing ratio according to the sub dividing ratio.

Spread spectrum clock generating circuit

Provided is a PLL circuit including automatic frequency control circuit and an operating method thereof. The voltage controlled oscillator is primarily controlled by an automatic frequency control circuit, and is secondarily controlled by a loop filter. The voltage controlled oscillator outputs a coarsely-tuned oscillation signal when primarily controlled, and outputs a finely-tuned oscillation signal when secondarily controlled. The PLL circuit can have a quick frequency fixing time, and output the oscillation signal having a broad and stable frequency. Moreover, the noise characteristic of the PLL circuit is enhanced.

Phase locked loop circuit including automatic frequency control circuit and operating method thereof

A phase-locked loop (PLL) circuit including a voltage-controlled oscillator (VCO) with a variable gain is provided. A phase frequency detector (PFD) detects a phase difference between a reference signal and a PLL feedback signal. A charge pump and a loop filter sequentially process an output signal of the PFD. A VCO has different gains according to a mode transition. A control voltage applied to the VCO is selected from an output signal of the loop filter and an additional control signal according to the mode transition.

Phase-locked loop circuit comprising voltage-controlled oscillator having variable gain

Provided are a switching circuit and a small-size high-efficiency direct current-to-direct current (DC-DC) converter for portable devices including the same. Using dynamic threshold-complementary metal oxide semiconductor (DT-CMOS) transistors having dynamic threshold voltages as a switching device, the switching circuit maintains a low threshold voltage in a normal mode to improve current drivability while reducing conduction loss, and maintains a high threshold voltage in a standby mode to minimize power consumption. When the switching circuit is employed in a DC-DC converter, power conversion efficiency can be improved by reducing conduction loss in the normal mode, and power consumption can be minimized in the standby mode. Consequently, the DC-DC converter can maximize a use time of a battery of a portable device and can be useful in power supplies of portable devices that are gradually being miniaturized.

Switching circuit and small-size high-efficiency DC-DC converter for portable devices including the same

Provided is a transformer-based oscillator which is suited to oscillate frequencies in multiple bands. An oscillator includes a transformer resonance unit and a plurality of complementary transistors. The transformer resonance unit includes a primary coil and a secondary coil corresponding to the primary coil. The plurality of complementary transistors have gates and drains between which both ends of the transformer resonance unit are respectively connected. Thus, the oscillator may operate in a differential mode or common mode according to the phase of the transformer resonance unit. Also, a complementary transistor constituting a multiband oscillation loop may be independently connected to both ends of the transformer resonance unit, and an oscillation loop of at least one band may be selected out of a multiband oscillation loop using a switch unit. Thus, the oscillator may be suited to oscillate resonance frequencies in multiple bands.

Oscillator

An LC voltage-controlled oscillator (VCO) is provided. The LC VCO includes an LC resonant circuit including at least one inductor whose both terminals are connected to output nodes and at least one capacitor connected in parallel with the inductor, and an amplifier circuit including at least one pair of switching transistors. Here, drains of the pair of switching transistors are connected to the output nodes respectively, and gates of the switching transistors are connected with the drains through a variable capacitance block exhibiting different characteristics according to an input signal.

LC voltage-controlled oscillator

Provided is a ring oscillator having an extended range of oscillation frequency by varactors coupled to delay cells even in a simple structure. The wide frequency range results from simply varying an oscillation frequency by control signals applied to the varactors. Since additional switches connected to the delay cells contribute to increase or decrease of the oscillation frequency range, the ring oscillator can conveniently be employed in various types of oscillation systems.

Ring oscillator having wide frequency range

Provided are a lock detection circuit and a lock detecting method. The lock detection circuit includes two delay devices, four flip-flops and two logic gates, and can accurately detect a lock state of a phase locked loop (PLL) circuit. Therefore, the lock detection circuit can be implemented in a simple structure, and as a result, the lock detection circuit can be compact in size and can consume less electric power. Also, the lock detecting method enables lock detection process to be simpler, so that a lock state can be detected within a short time period.

Lock detection circuit and lock detecting method

Provided is a low voltage frequency synthesizer using a boosting method for a power supply voltage of a charge pump. The low voltage frequency synthesizer includes a phase/frequency detector (PFD) that receives and compares a reference frequency and a feedback frequency to output a comparison signal, a charge pump that receives the comparison signal to output a current corresponding to the comparison signal, a low-pass filter (LPF) that generates a voltage corresponding to the output current of the charge pump, a voltage controlled oscillator (VCO) that receives the voltage of the LPF, amplifies the voltage to generate a boosting voltage, and outputs a frequency corresponding to the received voltage, and a DC converter that receives the boosting voltage of the VCO, converts the boosting voltage into a DC voltage, and applies the DC voltage as a power supply voltage of the charge pump. Since the supply voltage of the charge pump is provided from the LC-circuit-based VCO, the frequency synthesizer has superior characteristics such as a wide locking range, low phase noise, and the prevention of performance degradation caused by an external environment or process variations.

Low voltage frequency synthesizer using boosting method for power supply voltage of charge pump

Provided is a gain amplifier having a switched-capacitor structure capable of minimizing settling time, in which an input capacitor is connected to an input terminal during a first clock sampling an input signal, and thus an output terminal of the amplifier is reset in advance to an estimated output voltage value rather than 0 by the input capacitor. Accordingly, the slight move of the output terminal of the amplifier is sufficient to settle to a desired value in an amplification mode, so that slewing time can be reduced, and as a result, overall settling time and power consumption can be minimized.

Gain amplifier having switched-capacitor structure for minimizing settling time

Provided is a high-speed asynchronous digital signal level conversion circuit converting an input signal of a first voltage level into a signal of a second voltage level. The conversion circuit is able to operate at high speed by connecting first and second nodes, at which the input signal of the first voltage level is converted to the signal of the second voltage level, to a second power source voltage of the second voltage level for fast voltage level conversion when the voltage level of the input signal is changed.

High-speed asynchronous digital signal level conversion circuit

Provided are a pipeline Analog-to-Digital Converter (ADC) without a front-end Sample-and-Hold Amplifier (SHA) and a method of controlling the same. The method includes the steps of: simultaneously sampling, at an ADC and a residual signal generator included in a first stage, an analog input signal and respectively generating a first sampling value and a second sampling value; holding, at the residual signal generator, the second sampling value, and simultaneously amplifying and converting, at the ADC, the first sampling value into a corresponding digital code; and generating, at the residual signal generator, a residual signal using the digital code. The pipeline ADC and method of controlling the same minimize sampling mismatch caused by removing a front-end SHA, thereby ensuring stable performance without a front-end SHA. Since a front-end SHA is not used, it is possible to reduce chip size and power consumption, and improve the performance of the ADC.

Method of controlling pipeline analog-to-digital converter and pipeline analog-to-digital converter implementing the same

Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well corresponding to a substrate of a ggNMOS device. Thus, a trigger voltage of the SCR is reduced. In addition, two discharge paths are formed using two SCRs including PNP and NPN bipolar transistors. As a result, the ESD protection circuit can have greater discharge capacity.

Electrostatic discharge protection circuit using triple welled silicon controlled rectifier

Provided is an LC resonance voltage-controlled oscillator (VCO) used for a multi-band multi-mode wireless transceiver. In order to generate a multi-band frequency, a capacitor bank and a switchable inductor are included in the LC resonance voltage-controlled oscillator. The LC resonance voltage-controlled oscillator employs an adjustable emitter-degeneration negative resistance cell in place of tail current sources in order to compensate for non-uniform oscillation amplitude caused by the capacitor bank and prevent the degradation of a phase noise due to the tail current sources. The LC resonance voltage-controlled oscillator includes an inductor providing an inductance element partially determining the frequency of an oscillation wave; a discrete capacitor bank providing a capacitance element partially determining the frequency of the oscillation wave and being discretely determined by a control bit signal; and a discrete negative resistance cell providing a negative resistance element that is discretely determined by the control bit signal, to keep the amplitude of the oscillation wave constant.

Multi-band LC resonance voltage-controlled oscillator with adjustable negative resistance cell

A delta-sigma modulator having a first integrator for integrating an input signal; an analog-to-digital converter for converting the integrated signal into a digital signal; a delay circuit for delaying an output signal of the analog-to-digital converter; and a differential delay circuit for differentially delaying the output signal of the analog-to-digital converter. More particularly, the delta-sigma modulator has low distortion characteristics suitable for multi-bit fast operation, wherein a feedback signal is delayed by one clock period through the delay circuit and the differential delay circuit.

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Daejeon, South Korea

Kwi Dong Kim