Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies Ecbu IP (singapore) Pte. Ltd.

Kwee Chong Chang

Gek Yong Ng

Jia Peng

Qian Tao

Shan Jiang

Dominique Ho

Fun Kok Chow

Richard Baumgartner

Kah Weng Lee

Chee Heng Wong

Kok Keong Richard Lum

Richard Kok Keong Lum

Peng Siang Seet

Brian J Misek

A capacitive isolation system, capacitive isolator, and method of operating the same are disclosed. The capacitive isolation system is described to include a first semiconductor die and a second semiconductor die each having capacitive elements established thereon and positioned in a face-to-face configuration. An isolation layer is provided between the first and second semiconductor die so as to establish an isolation boundary therebetween. Capacitive coupling is used to carry information across the isolation boundary.

Isolator with reduced susceptibility to parasitic coupling

An isolation device having first and second semiconductor is disclosed. The first semiconductor die may be adapted to transmit a first signal to the second semiconductor die that is electrically isolated. The first semiconductor die may have a transmitter coupled to a modulator that modulates the first signal. The second semiconductor die may have a receiver having a counter and a control circuit. The control circuit may be adapted to determine an indication of the first signal by using the counter. In addition, an isolation system and a DC-DC feedback regulation control system having such control circuit are disclosed. Likewise, a method for conveying a first signal across an isolation barrier is disclosed. The method may comprise counting a received signal based on internal clock and determining an indication of the first signal from the counter's count value.

Isolation device and system

Various embodiments of systems for transmitting and receiving a plurality of signals across an isolation material are disclosed. In one embodiment, a first signal may be modulated into a first modulated signal. The first modulated signal is then modulated into a second modulated signal in accordance to a second signal using amplitude modulation. In another embodiment, a first signal and a second signal are modulated into a modulated signal before being modulated further using amplitude modulation. The detection of the modulated signal may be performed using a frequency detector and an amplitude detection circuit that are arranged in parallel. At least some of the apparatuses, circuits, systems and methods disclosed herein may be implemented using conventional CMOS design and manufacturing techniques to provide, for example, at least one or more integrated circuits.

Transmitting and receiving digital and analog signals across an isolator using amplitude modulation

Various embodiments of systems for transmitting and receiving digital and/or analog signals across a single isolator, solid state lighting systems, or DC/DC converter feedback regulation control systems are disclosed. In one embodiment, a first signal may be modulated into a first modulated signal. The first modulated signal is then modulated into a second modulated signal in accordance to a second signal. The second modulated signal is in turn, modulated into a third modulated signal in accordance to a third signal. At least some of the apparatuses, circuits, systems and methods disclosed herein may be implemented using conventional CMOS design and manufacturing techniques and processes to provide, for example, at least one or more integrated circuits.

Transmitting and receiving digital and analog signals across an isolator

Various embodiments of systems for transmitting and receiving digital and Various embodiments of systems for transmitting and receiving digital and/or analog signals across a single isolator, solid state lighting systems, or DC/DC converter feedback regulation control systems are disclosed. In one embodiment, the digital and analog signals may be modulated into a frequency modulated signal, and each pulse of the frequency modulated signal may be further encoded into a major pulse and a minor pulse. At least some of the circuits, systems and methods disclosed herein may be implemented using conventional CMOS design and manufacturing techniques and processes to provide, for example, a single integrated circuit or ASIC.

A galvanic isolator having a transmitting section and a receiving section is disclosed. The transmitting section includes a frame input circuit, a data encoder, and a data transmitter. The frame input circuit receives an input data frame that includes a plurality of input binary bits. The data encoder encodes the input binary bits to generate an encoded data frame that includes a sequence of encoded binary bits in which two successive encoded binary bits represent each input binary bit. The successive encoded binary bits representing a 1 are 01 or 10, and the successive encoded binary bits representing a 0 are 00 or 11. The sequences are chosen to maximize the number of transitions in the encoded data frame. A data receiver recovers the encoded data frame by examining successive pairs of encoded data bits using a clock that is reset on the edges in the encoded data frame.

Multi-channel galvanic isolator utilizing a single transmission channel

In an opto-isolator, a common mode pulse compensation circuit is provided that senses when a common mode pulse event occurs and that adds current to the LED drive current to compensate for a decrease in the LED drive current caused by the occurrence of the event. The common mode pulse compensation circuit is capable of operating effectively over a very wide range of common mode pulse slopes by automatically adjusting the amount of current that is added to the LED drive current based at least in part on the slope of the sensed common mode pulse. In addition, the common mode pulse compensation circuit is capable of being implemented with LEDs that operate at very low drive currents, which allows the power consumption requirements of the opto-isolator to be reduced.

Methods and apparatuses for performing common mode pulse compensation in an opto-isolator

Digital trimming logic is included in a microelectronic device of a type that produces an output signal in response to an input signal and a threshold signal. Trimming logic values are produced in response to a clock signal that is applied to the device in a trimming mode. The clock signal can be applied to a device pin that is used in normal operation to provide an output signal, thus allowing the pin to serve a dual function. The trimming logic changes the trimming logic value in response to the clock signal until the trimming logic value reaches a trim value at which the threshold signal is substantially equal to the input signal. The trimming logic then stores the trim value in a non-volatile memory and enters a locked mode in which further trimming is prevented and the device is ready for normal operation.

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Singapore, Singapore

Kwee Chong Chang