Samsung Electronics Co., Ltd.

Kwanyoung Oh

Sunpil Youn

Jiwon Park

Seungwook Lee

Haewon Lee

Donghyuk Park

Mihye Kim

An image sensor includes a first floating diffusion region, a second floating diffusion region adjacent to the first floating diffusion region in a first direction, a third floating diffusion region adjacent to the first floating diffusion region in a second direction that is perpendicular to the first direction and a fourth floating diffusion region adjacent to the second floating diffusion region in the second direction. A pad is disposed on the first and second floating diffusion regions. The pad at least partially overlaps the first and second floating diffusion regions. The image sensor includes an interconnection line and a first contact connecting the pad to the interconnection line. A first surface of the pad is disposed on the first floating diffusion region and the second floating diffusion region. A device isolation pattern defines the first, second, third and fourth floating diffusion regions.

Image sensor

A multiple-chip-package (MCP) has multiple chip groups and multiple package terminal groups for electrical connections in the MCP. Semiconductor chips of the same chip group are electrically connected to the package terminals of the same package terminal group, while package terminals of different chip groups are electrically connected to the package terminals of different package terminal groups.

Ball-grid-array package, electronic system and method of manufacture

A memory module includes a first multichip package including a first master chip and a first plurality of slave chips, and a second multichip package, the second multichip package including a second master chip and a second plurality of slave chips. A first through via passes through the first master chip and electrically connects to the first master chip to provide a supply voltage to the first master chip. A second through via passes through the first master chip without being electrically connected to provide a supply voltage to the first master chip. A first set of additional through vias pass through respective ones of the first plurality of slave chips and electrically connect to the respective ones of the first plurality of slave chips, wherein the second through via and first set of additional through vias are aligned to form a first stack of through vias.

Growing community of inventors

Gyeonggi-do, South Korea

Kwanyoung Oh