Xilinx, Inc.

Xilink, Inc.

Kwansuhk Oh

Raymond C Pang

Steven P Young

Trevor J Bauer

F Erich Goetting

Paul Ying-Fung Wu

Hsung Jai Im

Sunhom Paak

Bruce E Talley

P Hugo Lamarche

Patrick J McGuire

Boon Yong Ang

Himanshu J Verma

Robert M Ondris

An integrated circuit with an efuse having an efuse link includes a damage detection structure disposed in relation to the efuse so as to detect damage in the IC resulting from programming the efuse. Damage sensing circuitry is optionally included on the IC. Embodiments are used in evaluation wafers to determine proper efuse fabrication and programming parameters, and in production ICs to identify efuse programming damage that might create a latent defect.

Integrated circuit with fuse programming damage detection

A clock manager circuit includes a number of clock output blocks, each providing an independent output. Counter controlled delay devices (CCDs) are used in these clock output blocks. To achieve full cycle delays, the CCDs are placed in parallel with outputs of the CCD outputs driving set and reset terminals of a common latch. The parallel connection of the CCDs, as opposed to a series connection, offers an increase in maximum frequency and possibly fewer needed CCDs than if the CCDs are placed in series. In one embodiment, at least one of the CCDs includes a counter/compare circuit with a frequency divider enabling the frequency of the CCD to be varied relative to the common input clock.

Circuits and methods of using parallel counter controlled delay lines to generate a clock signal

An eFuse sensing circuit replaces the inverters used to provide the 'read' output state of a conventional eFuse circuit. The sensing circuit includes a comparator with one input coupled to the eFuse circuitry, and a second input coupled to a reference voltage generator circuit. The reference voltage generator circuit includes an internal resistor. Transistors of the sense circuit are provided to mimic the transistors of the eFuse circuit, so that variations of transistors due to process, voltage and temperature will be substantially the same. The resistor of the sense circuit is then effectively compared with the resistance of the eFuse by the comparator irrespective of temperature and process variations.

eFuse resistance sensing scheme with improved accuracy

An integrated circuit die (e.g., a programmable logic device (PLD) die) is manufactured that has the capability of being configured as at least two differently-sized family members. The IC die is tested prior to packaging. If a first portion of the IC die is fully functional, but a second portion includes a localized defect, then the IC die is packaged with a product selection code that configures the IC die to operate as only the first portion of the die. The second portion of the die is deliberately rendered non-operational. Therefore, the IC die can still be sold as a fully functional packaged IC.

Yield-enhancing methods of providing a family of scaled integrated circuits

Signal phase adjustment for duty cycle control is described. A first sample clock signal and a second sample clock signal are provided. A first phase signal and a second phase signal are generated responsive to the first sample clock signal, where the first phase signal is out of phase with respect to the second phase signal. The second sample clock signal configured to be swept in phase in relation to the first phase signal. A combined signal is generated where the combined signal has a duty cycle associated with the first phase signal and the second phase signal in combination. A first counter and a second counter are clocked responsive to the second sample clock signal to count. A first count from the first counter is divided by a second count from the second counter to obtain the duty cycle associated with the combined signal.

Signal adjustment for duty cycle control

An integrated circuit having a scalable boundary scan architecture. Logic elements, each including at least one data storage element, are arranged in rows and columns. A data distribution system couples the data storage elements together to form a boundary scan chain that traverses the columns in order, e.g., a first column, then a second column, and so forth, from top to bottom in each column. A clock distribution system is coupled to each of the data storage elements in the chain, and provides a clock signal to the first and second columns, again from top to bottom. The clock distribution system provides the clock signal to the top of the second column prior to providing it to the top of the first column. In some embodiments, an additional flip-flop is added to the boundary scan chain for each logic element, to increase the overall operating frequency of the scan chain.

Scalable columnar boundary scan architecture for integrated circuits

A multi-product integrated circuit die includes at least two different portions, of which at least one portion can be deliberately rendered non-operational in some manner (e.g., non-functional, inaccessible, and/or non-programmable) within the package. A selection code storage circuit stores a product selection code. A first value of the product selection code selects the option where both the first and second portions of the first die are operational. A second value of the product selection code selects the option where only the first portion of the first die is operational. The selection code storage circuit can include non-volatile memory or a fuse structure, or the product selection code can be configured as a package bonding option. The product selection code can also enable boundary scan for the operational portion of the die, and omit from the boundary scan chain any portions of the die that are deliberately rendered non-operational.

Multi-product die configurable as two or more programmable integrated circuits of different logic capacities

A trim unit includes a delay line and one or more individually selectable load elements. The delay line has a first end to receive an input clock signal, and has a second end to generate an output clock signal. Each load element includes a select transistor and a load capacitor coupled in series between the delay line and ground potential, and includes a filter circuit having an input to receive a select signal and having an output coupled to a gate of the select transistor. Upon assertion of each select signal, the filter circuit gradually charges the gate of the select transistor, which in turn causes the load element to gradually increase the phase-delay between the input and output clock signals.

Trim unit having less jitter

A delay circuit has a delay that is consistent under varying process and temperature conditions. The delay through a delay path is controlled by inserting resistors on the pull-up and pull-down paths of the delaying inverters. Each resistor has a resistance value that is determined by a varying a number of enabled similarly-sized transistors coupled in parallel across the resistor, rather than by varying the size of a single transistor. In one embodiment, a first transistor in each resistor is always enabled, while additional transistors are enabled using select signals. In one embodiment, the select signals are provided by configuration memory cells in a PLD. Other embodiments include additional delay paths and a multiplexer circuit that selects one of the delay paths. The described delay circuit is particularly useful in a DLL trim unit, where variations between resistors can cause jitter and locking problems in the DLL.

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San Jose, CA, United States of America

Kwansuhk Oh